MICHAEL HART, N.P.
Nursing at Oak St, San Jose, CA
License number
California 430931
Category
Nursing
Type
Family
Address
Address
100 Oak St, San Jose, CA 95110
Phone
(408) 295-0980
(408) 993-9833 (Fax)
(408) 284-2281
(408) 754-0450 (Fax)
(408) 993-9833 (Fax)
(408) 284-2281
(408) 754-0450 (Fax)
Professional information
Sr. Director, Advanced Technology, Xilinx Inc.
Position:
Sr. Director Advanced Technology, Advanced Architecture, Technology & Verification Group at Xilinx Inc.
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Xilinx Inc.
- San Jose, CA since Jan 1993
-
Sr. Director Advanced Technology, Advanced Architecture, Technology & Verification Group
Crosspoint Solutions Inc.
Aug 1992 - Jan 1993
-
Senior Device/Process Engineer
National Semiconductor
Oct 1987 - Aug 1992
-
Program Manager
Education:
University of Southampton 1981 - 1986
Ph.D., Electrical & Electronic Engineering University of Oxford 1978 - 1981
BA, Physics
Ph.D., Electrical & Electronic Engineering University of Oxford 1978 - 1981
BA, Physics
Languages:
Intermediate Spanish
Michael Hart, San Jose CA - NP (Nurse practitioner)
Specialties:
Nursing (Nurse Practitioner)
Address:
100 Oak St, San Jose 95110
(408) 295-0980 (Phone), (408) 993-9833 (Fax)
(408) 295-0980 (Phone), (408) 993-9833 (Fax)
Languages:
English
Michael A Hart, San Jose CA
Specialties:
Nurse Practitioner
Address:
100 Oak St, San Jose, CA 95110
5671 Santa Teresa Blvd, San Jose, CA 95123
5671 Santa Teresa Blvd, San Jose, CA 95123
Electro-Static Discharge Protection For Die Of A Multi-Chip Module
US Patent:
2012000, Jan 5, 2012
Filed:
Jun 30, 2010
Appl. No.:
12/828007
Inventors:
James Karp - Saratoga CA, US
Michael J. Hart - San Jose CA, US
Mohammed Fakhruddin - San Jose CA, US
Steven T. Reilly - Albuquerque NM, US
Michael J. Hart - San Jose CA, US
Mohammed Fakhruddin - San Jose CA, US
Steven T. Reilly - Albuquerque NM, US
Assignee:
XILINX, INC. - San Jose CA
International Classification:
H05K 7/00, H01R 43/00
US Classification:
361820, 29825
Abstract:
Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.