HONG C NGUYEN, O.D.
Optometry in San Jose, CA

7105442, Sep 12, 2006

May 22, 2002

10/154532

Hongching Shan - Cupertino CA, US
Kenny L. Doan - San Jose CA, US
Jingbao Liu - Sunnyvale CA, US
Michael S. Barnes - San Ramon CA, US
Hong D. Nguyen - San Jose CA, US
Christopher Dennis Bencher - San Jose CA, US
Christopher S. Ngai - Burlingame CA, US
Wendy H. Yeh - Mountain View CA, US
Eda Tuncel - Menlo Park CA, US
Claes H. Bjorkman - Mountain View CA, US

Applied Materials, Inc. - Santa Clara CA

H01L 21/44, H01L 21/31, H01L 21/469

438681, 438758

A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer () is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer () is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer () underlying the topmost masking layer () from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.