GLENN CLIFFORD STEINER
Pilots at Arbor Ave, Los Altos, CA

5369589, Nov 29, 1994

Sep 15, 1993

8/121990

Glenn C. Steiner - Los Altos CA

Trimble Navigation Limited - Sunnyvale CA

G06F 1550, G08G 1123, G01S 1300

364449

Apparatus for visually displaying simultaneously on one screen two variables that characterize the path followed by a land, marine or airborne vessel with reference to a preselected or ideal path that extends from a beginning point to an ending point. Using two distinguishable icons or other indicia for the two variables, the screen displays a single one-dimensional scale and displays the two indicia, each of which represents one of the following differences: (1) the difference between at least one of the two horizontal location coordinates for the present vessel location and for a nearest point on the preselected path; (2) the difference between the elevation coordinates for the present vessel location and for a nearest point on the preselected path; (3) the difference between the present horizontal bearing angle of the vessel path and the horizontal bearing angle along the preselected path at a nearest point on the preselected path; and (4) the difference between the present vertical bearing angle of the vessel path and the vertical bearing angle along the preselected path at a nearest point on the preselected path. Alternatively, the screen may display two one-dimensional scales with either two indicia, three indicia or two mutually exclusive sets of two indicia. Alternatively, two indicia may be used to define the size of a rectangle and the quadrant it appears in, for representation of the two indicia.

8006068, Aug 23, 2011

Apr 18, 2007

11/787926

Glenn C. Steiner - Los Altos CA, US

Xilinx, Inc. - San Jose CA

G06F 15/76

712 34

Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are provided. Data storage coupled to the general-purpose processor via the APU interface is provided for a fixed or low variable read latency access and a fixed write latency access to the data storage. A first instruction is passed to the general-purpose processor and to the APU interface. The first instruction is identified as part of a set of instructions accessible by the APU interface. The first instruction is used to write data into the data storage. A second instruction is passed to the general-purpose processor and to the APU interface. The second instruction is identified as part of the set of instructions accessible by the APU interface. The second instruction is used to read the data from the data storage, and the data is then output.

7298168, Nov 20, 2007

Apr 18, 2007

11/787813

Glenn C. Steiner - Los Altos CA, US

Xilinx, Inc. - San Jose CA

H03K 19/003

326 10, 326 9, 326 11

A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second portion of configuration memory cells that are un-programmed. The programmed and un-programmed configuration memory cells are grouped into voting groups, where each un-programmed configuration memory cell of each voting group is programmed with the identical configuration data as contained within the originally programmed configuration memory cell of each voting group. The logic values of each configuration memory cell of each voting group are monitored by voting circuits, which enforce a triple modular redundancy (TMR) validation policy. The logical validation results are then applied to control points to mitigate PLD configuration memory errors caused by anomalous events such as neutron induced SEUs.

6898434, May 24, 2005

Oct 30, 2001

10/021232

Salil Pradhan - Santa Clara CA, US
Glenn C. Steiner - Los Altos CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04Q007/20

4554561, 4554565, 455 412, 342450, 701200

An apparatus and method for the automatic positioning of information access points. An electronically connected individual (ECI) passes within range of a first information access point (IAP) and obtains location information. Subsequently, the ECI passes within range of a second IAP which hitherto does not have any location information. The location for this second IAP can be estimated based on the location obtained from the first IAP, elapsed time, and the individual's estimated velocity vector. As the ECI passes by a third IAP, the location, elapsed time, and estimated velocity vector data corresponding to the third IAP can be used to refine the location of the second IAP. Over time, the location of the second IAP can be successively refined as ECI's move between IAP's.

7236000, Jun 26, 2007

Oct 18, 2005

11/252682

Glenn C. Steiner - Los Altos CA, US

Xilinx, Inc. - San Jose CA

H03K 19/003

326 11, 326 10, 326 9, 326 37

A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second portion of configuration memory cells that are un-programmed. The programmed and un-programmed configuration memory cells are grouped into voting groups, where each un-programmed configuration memory cell of each voting group is programmed with the identical configuration data as contained within the originally programmed configuration memory cell of each voting group. The logic values of each configuration memory cell of each voting group are monitored by voting circuits, which enforce a triple modular redundancy (TMR) validation policy. The logical validation results are then applied to control points to mitigate PLD configuration memory errors caused by anomalous events such as neutron induced SEUs.

8058916, Nov 15, 2011

Apr 15, 2010

12/761035

Glenn C. Steiner - Los Altos CA, US

Xilinx, Inc. - San Jose CA

H03L 7/06

327156, 327147

A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation.

8005181, Aug 23, 2011

Oct 22, 2004

10/970968

Glenn C. Steiner - Los Altos CA, US

Xilinx, Inc. - San Jose CA

H03D 3/24

375373

A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noise phase region of the primary clock to produce an adjusted auxiliary clock.

5745866, Apr 28, 1998

Jan 9, 1996

8/584347

Glenn C. Steiner - Los Altos CA

Trimble Navigation Limited - Sunnyvale CA

G06F16500, G09G 532

701200

A system, method, and apparatus for displaying map information in a cardinal direction-up setting. In one embodiment, map information is displayed on a display terminal. Next, an icon representing the position and heading of an item with respect to the displayed map information is placed over the displayed map information. In the present invention, the map information is displayed in a cardinal direction-up setting corresponding to the heading of the icon. Thus, if the heading of the icon is directed in a substantially eastern direction, the map information is displayed in an east-up orientation. The present invention further includes hysteresis logic which regulates when a different cardinal direction is oriented upward.

5848376, Dec 8, 1998

Nov 13, 1997

8/969191

Glenn C. Steiner - Los Altos CA
Lloyd H. Banta - Palo Alto CA

Trimble Navigation Limited - Sunnyvale CA

G06G 778

701213

A Global Positioning System (GPS) receiving apparatus that is powered by a control or data interface signal from a computing apparatus. The GPS receiving apparatus includes a GPS receiver for receiving GPS satellite signals and providing GPS-derived location information and a converter for converting the interface signal to operating power signal for operating the GPS receiver. Optionally, the GPS receiver includes a power controller for controlling a duty cycle of the operating power in the GPS receiver in order to not exceed the power available from the interface signal. The interface signal is transmitted according to an interface standard such as RS232, RS422, or PC parallel.

6215498, Apr 10, 2001

Sep 10, 1998

9/150769

Andrew S. Filo - Cupertino CA
Mark P. Morgenthaler - Los Gatos CA
Glenn C. Steiner - Los Altos CA

Lionhearth Technologies, Inc. - CA

G06T 1500

345419

A system of networked terminal apparatus for creating a three dimensional animated work environment wherein terminal users of various levels of immersion are depicted as avatars in the virtual work environment and wherein actions and information of the terminal users is input into the virtual work environment through their corresponding avatars in order to perform complimentary, independent and cooperative tasks in parallel to create simultaneous sets of solutions to problems relating to command, control, communications, cognition and intelligence. In a preferred embodiment, the virtual work environment emulates an actual military command post, with all of the instruments and familiar surroundings emulated in function if not in form. The terminal users of the environment (i. e. , the commanders and staff) immerse in this environment via virtual reality displays (audio and video) and inputs (microphone, body encoders and pointing devices) connected to individual personal computers.