Inventors:
Young Woo Park - Los Angeles CA
Assignee:
Samsung Electronics Co., Ltd. - Suwon
International Classification:
H01L 218242
US Classification:
438253, 438254, 438396, 438397, 438692
Abstract:
A method of forming capacitor over bit line storage nodes in dynamic random access memory cell includes forming a multi-layered structure having at least two silicon oxide layers as a thick molding layer, e. g. , to a thickness of more than 8000. The at least two silicon oxide layers are disposed to have an etch speed of relatively lower-positioned silicon oxide layer to be relatively faster than that of relatively upper-positioned silicon oxide layer. Holes are then etched in the multi-layered structure, thereby reducing a width differential between the upper and lower layers.