WILLIAM OPPERMAN RICHARDS
Pilots at Trelling Wood Dr, Cary, NC

5786620, Jul 28, 1998

Mar 8, 1996

8/613110

William R. Richards - Cary NC
Michael W. Dennen - Raleigh NC

Thunderbird Technologies, Inc. - Research Triangle Park NC

H01L 2976, H01L 2994

257408

A Fermi-FET, including but not limited to a tub-FET, a contoured-tub Fermi-FET or a short channel Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivity type from the drain region. The drain pocket implant region acts as a drain field stop to reduce or prevent drain-to-source field reach-through. Reduced low drain field threshold voltage, significantly reduced drain induced barrier lowering and reduced threshold dependence on channel length may be obtained, resulting in higher performance in short channels.

4956306, Sep 11, 1990

Nov 3, 1988

7/266756

Robert T. Fuller - Durham NC
Joseph C. Tsang - Raleigh NC
William R. Richards - Cary NC

Harris Corporation - Melbourne FL

H01L 21265

437 34

A semiconductor material is overlayed with sequentially stacked layers including a protective layer, an affinity layer having an affinity for a second implant blocking material comprising tungsten, a first implant blocking layer and a masking layer having a first pattern. A portion of the first blocking layer not being masked is removed to expose a first portion of the affinity layer and a first dopant is implanted into the underlying semiconductor through the exposed first portion of the affinity layer. The mask is removed to expose the first blocking layer and a second blocking layer is formed from the second blocking material over the exposed first portion of the affinity layer but not over the exposed first blocking layer. The first blocking layer is removed to expose a second portion of the affinity layer which constitutes a second pattern. A second dopant is implanted into the underlying semiconductor through the exposed second portion of the affinity layer.

2006013, Jun 29, 2006

Dec 6, 2005

11/295105

William Richards - Cary NC, US
Mike Shen - Austin TX, US

H01L 29/94

257368000

A field effect transistor includes a strained silicon channel in a substrate, source/drain regions in the substrate at opposite ends of the strained silicon channel, a gate insulating layer on the strained silicon channel, and a gate on the gate insulating layer. The doping of the strained silicon channel, the doping of the substrate and/or the depth of the strained silicon channel are configured to produce nearly zero vertical electric field in the gate insulating layer and in the strained silicon channel surface at a threshold voltage of the field effect transistor. Moreover, the gate is configured to provide a gate work function that is close to a mid-bandgap of silicon. Accordingly, a Fermi-FET with a strained silicon channel and a gate layer with a mid-bandgap work function are provided. Related fabrication methods using epitaxial growth also are described.

2007000, Jan 4, 2007

Jun 26, 2006

11/426494

Mike Shen - Austin TX, US
William Richards - Cary NC, US

H01L 29/76

257288000, 257368000, 257E27060

Field effect transistor integrated circuits include field effect transistors in an integrated circuit substrate, such as a semiconductor substrate. A first one of the field effect transistors has a body effect that is substantially lower than that of a second one of the field effect transistors during operation of the first and second field effect transistors. The field effect transistors may be interconnected to form a circuit, and the body effect of the first field effect transistor is substantially lower than that of the second field effect transistor during operation of the circuit.