WILLIAM JAY BAGGENSTOSS
Pilots at Fothergill St, Boise, ID
License number
Idaho A0070971
Issued Date
Mar 2016
Expiration Date
Mar 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
1970 E Fothergill St, Boise, ID 83716
Professional information
Pattern Mask With Features To Minimize The Effect Of Aberrations
US Patent:
6803157, Oct 12, 2004
Filed:
Mar 1, 2002
Appl. No.:
10/090073
Inventors:
Pary Baluswamy - Boise ID
William A. Stanton - Boise ID
William J. Baggenstoss - Boise ID
William A. Stanton - Boise ID
William J. Baggenstoss - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03F 900
US Classification:
430 5
Abstract:
A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of âsub-resolutionâ size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e. g. , with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.
Methods Of Reducing Proximity Effects In Lithographic Processes
US Patent:
6120952, Sep 19, 2000
Filed:
Oct 1, 1998
Appl. No.:
9/164786
Inventors:
Christophe Pierrat - Boise ID
James E. Burdorf - Tualitin OR
William Baggenstoss - Boise ID
William Stanton - Boise ID
James E. Burdorf - Tualitin OR
William Baggenstoss - Boise ID
William Stanton - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03F 900
US Classification:
430 30
Abstract:
Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
Methods Of Reducing Proximity Effects In Lithographic Processes
US Patent:
6319644, Nov 20, 2001
Filed:
Feb 12, 2001
Appl. No.:
9/780407
Inventors:
Christophe Pierrat - Boise ID
James E. Burdorf - Tualitin OR
William Baggenstoss - Boise ID
William Stanton - Boise ID
James E. Burdorf - Tualitin OR
William Baggenstoss - Boise ID
William Stanton - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03F 900
US Classification:
430 30
Abstract:
Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
Methods Of Reducing Proximity Effects In Lithographic Processes
US Patent:
6284419, Sep 4, 2001
Filed:
Jan 24, 2001
Appl. No.:
9/769603
Inventors:
Christophe Pierrat - Boise ID
James E. Burdorf - Tualitin OR
William Baggenstoss - Boise ID
William Stanton - Boise ID
James E. Burdorf - Tualitin OR
William Baggenstoss - Boise ID
William Stanton - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03F 900
US Classification:
430 30
Abstract:
Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
Pattern Mask With Features To Minimize The Effect Of Aberrations
US Patent:
7105278, Sep 12, 2006
Filed:
Jul 23, 2004
Appl. No.:
10/896985
Inventors:
Pary Baluswamy - Boise ID, US
William A. Stanton - Boise ID, US
William J. Baggenstoss - Boise ID, US
William A. Stanton - Boise ID, US
William J. Baggenstoss - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03C 5/00, G03F 9/00
US Classification:
430311, 430 5, 430396
Abstract:
A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e. g. , with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.
Pattern Mask With Features To Minimize The Effect Of Aberrations
US Patent:
2006009, May 4, 2006
Filed:
Dec 19, 2005
Appl. No.:
11/305197
Inventors:
Pary Baluswamy - Boise ID, US
William Stanton - Boise ID, US
William Baggenstoss - Boise ID, US
William Stanton - Boise ID, US
William Baggenstoss - Boise ID, US
International Classification:
G03C 5/00, G03F 1/00
US Classification:
430005000, 430311000, 430313000, 430394000
Abstract:
A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.
Reticles And Methods Of Forming And Using The Same
US Patent:
7229724, Jun 12, 2007
Filed:
Aug 16, 2004
Appl. No.:
10/919059
Inventors:
William J. Baggenstoss - Boise ID, US
Byron N. Burgess - Boise ID, US
Erik Byers - Boise ID, US
William A. Stanton - Boise ID, US
Byron N. Burgess - Boise ID, US
Erik Byers - Boise ID, US
William A. Stanton - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03F 1/00, G03C 5/00
US Classification:
430 5, 430394
Abstract:
Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns have unresolvable patterns formed in the periphery areas of the reticle patterns. The unresolvable patterns are non-transparent with respect to patterning radiation. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.
Reticles And Methods Of Forming And Using The Same
US Patent:
6854106, Feb 8, 2005
Filed:
Aug 29, 2002
Appl. No.:
10/230950
Inventors:
William J. Baggenstoss - Boise ID, US
Byron N. Burgess - Boise ID, US
Erik Byers - Boise ID, US
William A. Stanton - Boise ID, US
Byron N. Burgess - Boise ID, US
Erik Byers - Boise ID, US
William A. Stanton - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F017/50
US Classification:
716 21, 716 19
Abstract:
Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have sub-resolution patterns or a transmissive block fill formed in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.
Method Of Forming Pixel Cell Having A Grated Interface
US Patent:
8101454, Jan 24, 2012
Filed:
Dec 5, 2005
Appl. No.:
11/293245
Inventors:
William J. Baggenstoss - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/302, H01L 21/31, H01L 31/0232, H01L 31/0236
US Classification:
438 71, 438 72, 257437, 257E21214, 257E2124, 257E3112, 257E3113
Abstract:
A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface.
Pixel Cell Having A Grated Interface
US Patent:
7880255, Feb 1, 2011
Filed:
Jul 19, 2004
Appl. No.:
10/893276
Inventors:
William J. Baggenstoss - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 31/0236, H01L 31/0352
US Classification:
257436, 257466, 257E31038
Abstract:
A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface.