DAVID EDWARDS BECKER
Pilots at Sawmill Way, Boise, ID

6492279, Dec 10, 2002

Jan 27, 2000

09/492738

David S. Becker - Boise ID
Bradley J. Howard - Boise ID
Kevin G. Donohoe - Boise ID

Micron Technology, Inc. - Boise ID

H01L 21302

438714, 438723, 438724

A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0. 3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas. Such plasma etching is conducted under conditions effective to produce at least that portion of the one feature pattern in the feature layer formed during the one etching segment to have a sidewall taper, if any, of less than or equal to 5° and an organic masking layer top outer surface roughness proximate the feature pattern at a conclusion of the etching segment which is characterizable by an average value less than 100 Angstroms. Such value is determinable by scanning electron microscopy as an average maximum size of all surface discernible objects of the patterned masking layer as measured and averaged along any 0.

6812154, Nov 2, 2004

Oct 17, 2002

10/273851

David S. Becker - Boise ID
Bradley J. Howard - Boise ID
Kevin G. Donohoe - Boise ID

Micron Technology, INC - Boise ID

H01L 21302

438714, 438723, 438724

A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0. 3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas. Such plasma etching is conducted under conditions effective to produce at least that portion of the one feature pattern in the feature layer formed during the one etching segment to have a sidewall taper, if any, of less than or equal to 5° and an organic masking layer top outer surface roughness proximate the feature pattern at a conclusion of the etching segment which is characterizable by an average value less than 100 Angstroms. Such value is determinable by scanning electron microscopy as an average maximum size of all surface discernible objects of the patterned masking layer as measured and averaged along any 0.

5753565, May 19, 1998

Mar 12, 1996

8/614989

David S. Becker - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2128

438586

A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

5869403, Feb 9, 1999

Mar 14, 1997

8/818629

David S. Becker - Boise ID
Mark E. Jost - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2100

438738

A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area. According to one preferred aspect of the invention, the first oxide layer is formed from decomposition of tetraethyloxysilane (TEOS) and the second oxide layer comprises borophosphosilicate glass (BPSG). According to another preferred aspect of the invention, the second etch is an isotropic etch using an aqueous solution comprising fluorine having less than or equal to about 10% by weight of an etch rate changing surfactant which etches the second oxide layer at a slower rate than the first oxide layer.

6153501, Nov 28, 2000

May 20, 1998

9/082083

David S. Becker - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2128

438585

A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

5498570, Mar 12, 1996

Sep 15, 1994

8/306907

David S. Becker - Boise ID

Micron Technology Inc. - Boise ID

H01L 2144

437187

A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

6015760, Jan 18, 2000

Aug 4, 1997

8/905891

David S. Becker - Boise ID
Guy T. Blalock - Boise ID
Fred L. Roe - San Jose CA

Micron Technology, Inc. - Boise ID

H01L 21302

438714

A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

5899749, May 4, 1999

Mar 18, 1997

8/820301

David S. Becker - Boise ID
Guy T. Blalock - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2100

438714

A method of etching an oxide/poly/oxide sandwich structure in which both oxide layers are anisotropically etched, and the poly layer is also isotropically etched to recess the poly from the edge of the contact walls. The oxide etch can be done using oxide to nitride etch stop technology. The process is an in situ etch, that is, a single parallel plate plasma reactor is employed.

7074724, Jul 11, 2006

Jul 9, 2004

10/888255

Kevin G. Donohoe - Boise ID, US
David S. Becker - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/302

438714, 438720, 438723, 438724, 438734, 438740

A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous-etchant.

5691246, Nov 25, 1997

May 13, 1993

8/060902

David S. Becker - Boise ID
Guy T. Blalock - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2170

437225

A method of etching an oxide/poly/oxide sandwich structure in which both oxide layers are anisotropically etched, and the poly layer is also isotropically etched to recess the poly from the edge of the contact walls. The oxide etch can be done using oxide to nitride etch stop technology. The process is an in situ etch, that is, a single parallel plate plasma reactor is employed.