William A. Rogers Ph.D.
Engineering at Cercis Cv, Austin, TX

5383194, Jan 17, 1995

Nov 6, 1992

7/973069

Mark D. Sloan - Princeton IN
William A. Rogers - Austin TX
Srihari Shoroff - Austin TX

University of Texas System Board of Regents - Austin TX

G11C 2900

371 221

An integrated logic circuit according to the present invention includes a plurality of logic circuit elements, such as field effect transistors, for performing a combinational logic function, and at least one test controlled-impedance element for loading the logic circuit and causing a first digital output signal to be produced when the impedance of a logic circuit element under test is within a predetermined range and produce another digital output signal when the impedance of the logic circuit element under test is outside the predetermined range. The test controlled-impedance elements typically comprise field effect transistors and are sized in accordance with a series of constraints. The constraints are obtained by considering the operation of the circuit under various impedance fault conditions (high, low and intermediate) and deriving a series of size relationships between the impedance values of the logic circuit and test elements. The impedance faults capable of being detected include the conventional stuck-on (LIF) arid stuck-off (HIF) impedance faults and also intermediate impedance faults (IHIF, ILIF) caused by a too high or too low an impedance in a transistor's on- and off-state modes of operation, respectively.

5519713, May 21, 1996

Dec 2, 1993

8/161057

SangHyeon Baeg - Austin TX
William A. Rogers - Austin TX

The University of Texas System - Austin TX

G01R 3128

371 221

An integrated circuit includes a plurality of interconnected circuit modules having memory elements and logic elements therein. The modules collectively perform the operations of the integrated circuit. However, rather than testing the entire circuit and limiting the degree of fault coverage, individual modules can be tested on a module by module basis. To facilitate testing at the module level, the circuit includes a plurality of control cells connected to respective ones of the modules. Each of the control cells preferably includes a shift register latch for retaining a data signal corresponding to whether the respective module is to be sequentially tested or temporarily disabled. The control cells further comprise a pass-through transistor network for passing the system clock to one or more of the modules under test and for withholding the clock from the modules not under test. The method of the present invention includes steps for disabling one or more modules which are not under test and enabling those modules which are to be tested.

8583687, Nov 12, 2013

May 15, 2012

13/472271

Christopher M. Piedmonte - Ceder Park TX, US
William A. Rogers - Austin TX, US

Algebraix Data Corporation - Austin TX

G06F 17/30

707776, 707736, 707737, 707769, 707802

Systems and methods for storing and accessing data. Example embodiments may perform optimization based on patterns of requests received by the system and relations between data sets identified by the system. Example embodiments may identify restrictions on a data set based on a different data set. Conditions for automatically algebraically partitioning the data set based on a constituent of a different data set may be evaluated, including evaluation of the relationship between the data sets and identification of a pattern of statements restricting the data set using the same logical structure. If the conditions are met, component data sets and a partition data set may be algebraically defined based on ranges applied to constituent(s) of the other data set. The component data sets may also be realized in storage to physically partition the data set.

2007010, May 3, 2007

Nov 1, 2005

11/264416

William Rogers - Austin TX, US
Joseph Barta - Austin TX, US

G06F 11/00

714038000

The present disclosure provides methods for testing a software application using the natural input flow of the application. In one respect, a method includes observing the software application under test to determine a current, active input site of the application. The method generates a stimulus for the current, active input site based on the current execution state of the application and applies the stimulus to the current, active input site. The response of the stimulus may be evaluated. In one respect, the response may be evaluated prior to and after the stimulus is applied.