Brian J. Vicknair
Engineering at Spurlock Dr, Austin, TX
License number
Louisiana EI.0007494
Issued Date
Jan 27, 1981
Expiration Date
Mar 31, 2018
Category
Civil Engineer
Address
Address
7112 Spurlock Dr, Austin, TX 78731
Professional information
Brian Vicknair - Austin, TX
Work:
Gold Source, LLC
Business Consultant IBM
Alliance Technology Manager IBM
Opportunity Development Manager IBM
Systems Product Marketing Manager IBM
Software Marketing Manager IBM
e-business Solutions Marketing IBM
Executive Briefing Center Consultant IBM
Microprocessor Development Engineer IBM
Manufacturing Test Engineer Motorola
Semiconductor Product Engineer
Business Consultant IBM
Alliance Technology Manager IBM
Opportunity Development Manager IBM
Systems Product Marketing Manager IBM
Software Marketing Manager IBM
e-business Solutions Marketing IBM
Executive Briefing Center Consultant IBM
Microprocessor Development Engineer IBM
Manufacturing Test Engineer Motorola
Semiconductor Product Engineer
Education:
George Washington University - Washington, DC
Master's in Project Management Louisiana State University - Baton Rouge, LA
Master of Business Administration Louisiana State University - Baton Rouge, LA
B.S. in Electrical Engineering
Master's in Project Management Louisiana State University - Baton Rouge, LA
Master of Business Administration Louisiana State University - Baton Rouge, LA
B.S. in Electrical Engineering
Skills:
Presentations, Program Management, Logic Design, Microprocessor Architecture and Design, Strategic Alliances, Product Marketing, Windows, Systems Performance and Architecture, Negotiations, Product Management, Unix shell scripts, Storage Sub-systems, Communications, Project Management, Semiconductors, Unix Systems Administration (AIX), Management, Business Development, Virtualization, Enterprise Software, High Availability, Competitive Analysis, Cloud Computing, Solution and Enterprise Architecture
Senior Engineer At Ibm
Location:
Austin, Texas Area
Industry:
Information Technology and Services
Method And System For Efficient Maintenance Of Data Coherency In A Multiprocessor System Utilizing Cache Synchronization
US Patent:
5848283, Dec 8, 1998
Filed:
Jan 29, 1993
Appl. No.:
8/010900
Inventors:
Charles Roberts Moore - Austin TX
John Stephen Muhich - Austin TX
Brian James Vicknair - Austin TX
John Stephen Muhich - Austin TX
Brian James Vicknair - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
395800
Abstract:
A method and system are efficiently maintaining data coherency in a multiprocessor data processing system having multiple processors coupled together via common bus. Each time an attempted modification is made to selected data by one of the processors, a multistate bus synchronization flag is established within the initiating processor. A bus operation request which is appropriate for the type of data modification is then issued from a cache associated with the initiating processor to a memory queue associated therewith. The bus operation request is then transmitted onto the common bus from the memory queue on an opportunistic basis, permitting additional cache operations to occur during the pendency of the bus operation request. A successful assertion of the bus operation request, indicating no coherency problems exist with respect to other processors, results in an alteration of the state of the multistate bus synchronization flag, permitting modification of the selected data. A failure to successfully assert the bus operation request will result in the automatic reissue of the bus operation request, greatly enhancing the ability of the system to maintain data coherency.