Walter John Dauksher
Engineers at Ashton Ct, Fort Collins, CO

License number

Colorado 33456

Issued Date

Feb 12, 1999

Renew Date

Nov 1, 2015

Expiration Date

Oct 31, 2017

Type

Professional Engineer

Address

6106 Ashton Ct, Fort Collins, CO 80525

Professional information

Engineer At Avago Technologies

Position:

Engineer at Avago Technologies

Location:

Fort Collins, Colorado Area

Industry:

Semiconductors

Work:

Avago Technologies - Engineer Agilent Technologies 2000 - 2005 - Reliability Engineer Hewlett-Packard 1998 - 2000 - Reliability Engineer Boeing Commercial Airplanes 1990 - 1998 - Structural Engineer Rocketdyne 1988 - 1990 - Structural Engineer

Education:

University of Washington 1992 - 1998
PhD, Mechanical Engineering Colorado State University 1986 - 1988
MS, Mechanical Engineering Lafayette College 1982 - 1986
BS, Mechanical Engineering

Device For Enhancing The Local Cooling Of Electronic Packages Subject To Laminar Air Flow

US Patent:

6661666, Dec 9, 2003

Filed:

Sep 24, 2002

Appl. No.:

10/253961

Inventors:

Walter J. Dauksher - Fort Collins CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H05R 720

US Classification:

361719, 361690, 361704, 361718, 361720, 174 161, 174 163, 257721, 257722, 165 803, 165185

Abstract:

A device having features for enhancing the cooling of an electronic package subject to laminar air flow. The features include a bluff body, located adjacent the electronic package and within the laminar air flow, for creating turbulence in the air flow to enhance the cooling of the package. The turbulence creates a greater cooling effect of the air flow on the electronic package, and the bluff body can include a rod or other structure mounted adjacent the electronic package. The bluff body can also be mounted on the electronic package or on a heat sink mounted on top of the package.

Trace Design To Minimize Electromigration Damage To Solder Bumps

US Patent:

7659622, Feb 9, 2010

Filed:

Jul 18, 2007

Appl. No.:

11/779833

Inventors:

Walter J. Dauksher - Fort Collins CO, US
Dennis H. Eaton - Loveland CO, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H01L 29/40, H01L 23/48, H01L 23/485, H01L 23/52

US Classification:

257737, 257E23021, 257774, 257775, 257789, 438612

Abstract:

A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by dividing current carrying traces into a plurality of sub-traces with known resistances such that each sub-trace distributes a known amount of current to the pad of the integrated circuit. The multiple sub-traces connect to the pad and are placed to obtain a desired uniformity in the incoming current distribution. Width and/or length adjustments could be made to each of the plurality of sub-traces to obtain the desired resistances.

System And Method For Fabricating A Laminate Structure

US Patent:

2013010, May 2, 2013

Filed:

Nov 2, 2011

Appl. No.:

13/287323

Inventors:

Walter J. Dauksher - Fort Collins CO, US
Adam Gallegos - Fort Collins CO, US

International Classification:

B32B 41/00, B32B 37/02

US Classification:

156 64, 156378

Abstract:

A method for fabricating a laminate structure includes providing a laminate core, forming at least one laminate layer on each opposing side of the laminate core, the laminate core and the at least one laminate layer on each opposing side of the laminate core forming a laminate structure, determining an out-of-plane displacement for the laminate structure at a temperature of interest, the out-of-plane displacement corresponding to warpage, and if the warpage exceeds a predetermined value, modifying at least one of the laminate layers to reduce the warpage.