THINH TRAN, DDS
Dentist at Mclaughlin Ave, San Jose, CA
License number
California 62782
Category
Dentist
Type
Dentist
Address
Address
967 Mclaughlin Ave, San Jose, CA 95122
Phone
(408) 677-7308
Organization information
See more information about THINH TRAN at bizstanding.comThinh Tran
1590 Berryessa Rd, San Jose, CA 95133
Status:
Inactive
Industry:
Nonclassifiable Establishments
Owner:
Tran Tin Owner, inactive
Professional information
Flip Chip Trace Library Generator
US Patent:
6526540, Feb 25, 2003
Filed:
Jan 8, 2001
Appl. No.:
09/756506
Inventors:
Eric Fong - Cupertino CA
Thinh Tran - San Jose CA
Mike Teh-An Liang - Milpitas CA
Thinh Tran - San Jose CA
Mike Teh-An Liang - Milpitas CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 1, 716 3
Abstract:
A method of generating a trace library includes the steps of receiving as inputs a plurality of technology dependent parameters and a trace template and generating a trace layout from the inputs.
Test Pin Reduction Using Package Center Ball Grid Array
US Patent:
2009016, Jun 25, 2009
Filed:
Dec 20, 2007
Appl. No.:
12/004131
Inventors:
Anwar Ali - San Jose CA, US
Thinh Tran - San Jose CA, US
Wilson Choi - San Jose CA, US
Thinh Tran - San Jose CA, US
Wilson Choi - San Jose CA, US
International Classification:
G01R 31/26, G06F 17/50
US Classification:
324765, 716 4
Abstract:
An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.
Structuring Method
US Patent:
2003002, Jan 30, 2003
Filed:
Jul 27, 2001
Appl. No.:
09/916710
Inventors:
Juliana Arifin - , US
Thinh Tran - San Jose CA, US
Thinh Tran - San Jose CA, US
International Classification:
G03F007/20
US Classification:
430/394000, 430/312000, 430/313000, 430/318000
Abstract:
The invention provides a structuring method, in particular for stepped wafer or die surfaces. The method includes photolithographically exposing a pattern comprising at least a first pattern portion and a second pattern portion onto a surface, said surface comprising at least a first surface portion at which a tangential plane to the surface extends in a first plane and a second surface portion at which a tangential plane to the surface extends in a second plane not coinciding with the first plane. The method comprises a first exposure step, in which the first pattern portion is exposed. Therein, the first pattern portion is focused into a first focal plane. The method further comprises a second exposure step, in which the second pattern portion is exposed. Therein, the second pattern portion is focused into a second focal plane which is different from the first focal plane.