ROBERT ALAN GLENN
Pilots at 20 St, Boulder, CO
License number
Colorado A2493747
Issued Date
Jun 2016
Expiration Date
Jun 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
850 20Th St APT 603, Boulder, CO 80302
Personal information
See more information about ROBERT ALAN GLENN at radaris.comName
Address
Phone
5462 Apaloosa Dr, Colorado Spgs, CO 80923
529 Marquette Dr, Colorado Spgs, CO 80911
401 E 12Th St, Rifle, CO 81650
1011 Pierce St, Denver, CO 80214
421 Coronado Dr, Sedalia, CO 80135
Professional information
System And Method For Controlling Central Processing Unit Power Based On Inferred Workload Parallelism
US Patent:
2011014, Jun 16, 2011
Filed:
Nov 11, 2010
Appl. No.:
12/944140
Inventors:
Bohuslav Rychlik - San Diego CA, US
Robert A. Glenn - Boulder CO, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Steven S. Thomson - San Diego CA, US
Robert A. Glenn - Boulder CO, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Steven S. Thomson - San Diego CA, US
International Classification:
G06F 1/32
US Classification:
713323
Abstract:
A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.
System And Method For Asynchronously And Independently Controlling Core Clocks In A Multicore Central Processing Unit
US Patent:
2011014, Jun 16, 2011
Filed:
Nov 11, 2010
Appl. No.:
12/944321
Inventors:
Bohuslav Rychlik - San Diego CA, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Steven S. Thomson - San Diego CA, US
Robert A. Glenn - Boulder CO, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Steven S. Thomson - San Diego CA, US
Robert A. Glenn - Boulder CO, US
International Classification:
G06F 1/04
US Classification:
713600
Abstract:
A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.