QI WANG
Medical Practice at Park Ave, San Jose, CA
License number
California 511507-06
Category
Medical Practice
Type
Reflexologist
Address
Address
1449 Park Ave STE 1, San Jose, CA 95126
Phone
(408) 888-1635
(408) 261-1111 (Fax)
(408) 261-1111 (Fax)
Personal information
See more information about QI WANG at radaris.comName
Address
Phone
1025 Huntington Dr, Arcadia, CA 91007
20689 Azalea Terrace Rd, Riverside, CA 92508
1250 Valley Quail Cir, San Jose, CA 95120
125 Mahogany Ln, Union City, CA 94587
1405 Phelps Ave, San Jose, CA 95117
Professional information
Systems And Methods For Correcting High Order Aberrations In Laser Refractive Surgery
US Patent:
2013019, Jul 25, 2013
Filed:
Jul 20, 2012
Appl. No.:
13/554276
Inventors:
Anatoly Fabrikant - Fremont CA, US
Guang-ming Dai - Fremont CA, US
Dimitri Chernyak - Sunnyvale CA, US
Ben Logan - Los Gatos CA, US
David Hindi - Morgan Hill CA, US
Qi Wang - San Jose CA, US
Guang-ming Dai - Fremont CA, US
Dimitri Chernyak - Sunnyvale CA, US
Ben Logan - Los Gatos CA, US
David Hindi - Morgan Hill CA, US
Qi Wang - San Jose CA, US
Assignee:
AMO Manufacturing USA, LLC - Santa Ana CA
International Classification:
A61F 9/008
US Classification:
606 5, 606 4
Abstract:
Optical correction methods, devices, and systems reduce optical aberrations or inhibit refractive surgery induced aberrations. Error source control and adjustment or optimization of ablation profiles or other optical data address high order aberrations. A simulation approach identifies and characterizes system factors that can contribute to, or that can be adjusted to inhibit, optical aberrations. Modeling effects of system components facilitates adjustment of the system parameters.
Behavioral Level Observability Analysis And Its Applications
US Patent:
6728945, Apr 27, 2004
Filed:
Feb 26, 2001
Appl. No.:
09/793309
Inventors:
Qi Wang - San Jose CA
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 18, 716716, 716 17
Abstract:
A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.
Method And Mechanism For Implementing Electronic Designs Having Power Information Specifications Background
US Patent:
8516422, Aug 20, 2013
Filed:
Jun 14, 2010
Appl. No.:
12/815239
Inventors:
Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716109, 716111, 716120, 716123, 716133, 716127, 716136, 703 16
Abstract:
A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.
Method And Mechanism For Rtl Power Optimization
US Patent:
7007247, Feb 28, 2006
Filed:
May 24, 2002
Appl. No.:
10/155323
Inventors:
Qi Wang - San Jose CA, US
Sumit Roy - Milpitas CA, US
Sumit Roy - Milpitas CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 3, 716 7, 716 6, 716 18
Abstract:
The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.
Selection Of Cells From A Multiple Threshold Voltage Cell Library For Optimized Mapping To A Multi-Vt Circuit
US Patent:
7653885, Jan 26, 2010
Filed:
May 8, 2007
Appl. No.:
11/746026
Inventors:
Sourav Nandy - Ghaziabad, IN
Qi Wang - San Jose CA, US
Qi Wang - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 1, 716 3, 716 4, 716 5, 716 18, 703 13, 703 14
Abstract:
A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.
Optimized Mapping Of An Integrated Circuit Design To Multiple Cell Libraries During A Single Synthesis Pass
US Patent:
7530047, May 5, 2009
Filed:
Jun 5, 2006
Appl. No.:
11/447683
Inventors:
Qi Wang - San Jose CA, US
Ranganathan Sankaralingam - Noida, IN
Ranganathan Sankaralingam - Noida, IN
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 17, 716 3
Abstract:
A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.
High Level Ic Design With Power Specification And Power Source Hierarchy
US Patent:
7954078, May 31, 2011
Filed:
Jun 29, 2007
Appl. No.:
11/771953
Inventors:
Qi Wang - San Jose CA, US
Pinhong Chen - Saratoga CA, US
Mitchell W. Hines - San Jose CA, US
Pinhong Chen - Saratoga CA, US
Mitchell W. Hines - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716127, 716106, 716109, 716111, 716120, 716133
Abstract:
A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.
Method And Mechanism For Implementing Electronic Designs Having Power Information Specifications Background
US Patent:
RE44479, Sep 3, 2013
Filed:
Jun 12, 2012
Appl. No.:
13/494363
Inventors:
Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghoa Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Mitchell W. Hines - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghoa Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Mitchell W. Hines - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716105, 716102, 716103, 703 14
Abstract:
A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
Method And System For Conducting A Low-Power Design Exploration
US Patent:
7673276, Mar 2, 2010
Filed:
Oct 26, 2006
Appl. No.:
11/588927
Inventors:
Qi Wang - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 18
Abstract:
Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding to the RTL netlist, generating one or more low-power RTL netlists using the corresponding one or more power requirement files and the RTL netlist, and conducting low-power design explorations using the one or more low-power RTL netlists.
Method And Mechanism For Implementing Electronic Designs Having Power Information Specifications Background
US Patent:
7739629, Jun 15, 2010
Filed:
Oct 30, 2006
Appl. No.:
11/590657
Inventors:
Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 2, 716 7, 703 14
Abstract:
A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.