PETER DEANE
Pilots at Sunshine Vly Rd, Moss Beach, CA

7809221, Oct 5, 2010

May 2, 2007

11/743627

Peter Deane - Moss Beach CA, US

Poa Sana Liquidating Trust - Mountain View CA

G02B 6/32, G06F 3/042

385 33, 385 12, 385 14, 385 93, 385901, 345176

An optical based input touch display device with high resolution shadow detection using the linear splitting of waveguides among transmit and receive lenses and grey-scale calculations for shadow edge and center detection is disclosed. The apparatus includes a light source and a transmit waveguide optically coupled to the light source. The transmit waveguide includes a plurality of transmit waveguide grooves coupled to a plurality of groups of shared transmit lenses respectively. The plurality of groups of transit lenses, which are configured to generate a plurality of collimated light beams from the light source. A receive waveguide is also provided having a plurality of receive waveguide grooves coupled to a plurality of groups of shared receive lenses. The plurality of groups of receive lenses are configured to receive the plurality of collimated light beams. A photodiode array including a plurality of photodiodes are optically coupled to the plurality of receive waveguide grooves respectively.

7842544, Nov 30, 2010

Jun 5, 2009

12/479713

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/66, H01L 21/00, H01L 21/50, H01L 21/48

438106, 438 15, 438 25, 438 51, 438107, 438108, 257E21499, 257E21536, 257E21538, 257E21705

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure.

7321606, Jan 22, 2008

Dec 9, 2003

10/731965

Hsin-Ho Wu - Santa Clara CA, US
Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

H01S 3/00

372 381, 372 3801, 372 3802, 372 29021, 372 29011, 372 33

A method includes a scheme for trimming and compensation for a laser emitter in a fiber optic link. Data models of laser performance are provided and used to determine a base power level. It is then confirmed that the base power level is satisfactory. If necessary, adjustments are made to a set of user specified performance parameters until a satisfactory base power level is obtained. Then a table or relation of temperatures and associated current and target average optical power values is generated such that they can be used to regulate laser emitter performance over a range of temperature. Additionally, fiber optic links capable of trimming and compensation are also disclosed.

7843056, Nov 30, 2010

Feb 20, 2009

12/390349

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/04, H01L 23/12, H01L 23/053, H01L 23/34

257698, 257415, 257700, 257713, 257723, 257724, 257E21499, 257E21506, 257E21536, 257E21705

In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques.

7369724, May 6, 2008

Oct 3, 2006

11/542816

Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

G02B 6/32, G02B 6/26, G02B 6/42, G06F 3/042

385 33, 385 31, 385 38, 345173, 345175, 345176

A polymer waveguide assembly. The assembly includes a polymer waveguide have a plurality of waveguide cores and an associated plurality of lenses respectively. The assembly also includes a molded lens structure having a support region, a primary refractive surface and a secondary refractive lens. The polymer waveguide is positioned onto the support surface of the molded lens structure so that the waveguide lenses are in optical alignment with the primary refractive lens and the secondary refractive lens of the molded waveguide structure. The lenses of the polymer waveguide are capable of collimating in the X and Y directions respectively. The primary refractive lens and the secondary refractive lens are both capable of collimating light in the Z direction. With this arrangement, a substantial; portion of the light passing through the secondary lens toward the waveguide cores is within the acceptance angle of the plurality of waveguides lenses respectively. The secondary lens thus creates a shallow angle of convergence relative to the input of the plurality of lenses of the waveguide.

2011011, May 19, 2011

Jan 25, 2011

13/013563

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Peter Deane - Moss Beach CA, US
Reda R. Razouk - Sunnyvale CA, US

NATIONAL SEMICONDUCTOR CORPORATION - Santa Clara CA

H01L 23/522, H01L 21/56, H01L 21/768

257698, 438127, 438622, 257E23142, 257E21502, 257E21575

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

7898068, Mar 1, 2011

Jun 5, 2009

12/479709

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/02, H01L 23/12, H01L 23/053, H01L 23/34

257678, 257700, 257713, 257717, 257718, 257720, 257E21499, 257E21502, 257E21506, 257E21536, 257E21576

Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

7901981, Mar 8, 2011

Jun 5, 2009

12/479707

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/66, H01L 21/50, H01L 21/48, H01L 21/44

438106, 438 15, 438107, 438108, 438 25, 438 51, 257E21499, 257E21536, 257E21538, 257E21705

Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed.

7031576, Apr 18, 2006

Jul 25, 2003

10/627437

Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

G02B 6/30

385 49, 385 88

A connectorized silicon bench and ferrule that aids in the passive alignment of optical fibers to optical components on the bench. The apparatus includes a bench having an optical component, a groove formed in the bench, the groove configured to accommodate an optical fiber; and a ferrule, including a recess region to accommodate the optic fiber when the ferrule is mounted onto the bench. The groove and the ferrule cooperate to passively align the optical fiber and the optical component on the bench. A connector sleeve, which accommodates the silicon bench and ferrule, includes a receptacle that is configured to receive a plug-in connector which optically couples the optical fiber to an optical network or link.

7901984, Mar 8, 2011

Jun 5, 2009

12/479715

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Peter Deane - Moss Beach CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/66, H01L 21/50, H01L 21/48, H01L 21/44

438107, 438120, 438121, 438126, 438637, 438622, 257E21499, 257E21502, 257E21575

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers.