MICHAEL R ALLEN
Electrician at Abbott Dr, Austin, TX

5671370, Sep 23, 1997

Mar 25, 1996

8/622651

Michael Scott Allen - Austin TX
Ravi Kumar Arimilli - Round Rock TX
John Michael Kaiser - Cedar Park TX
William Kurt Lewchuk - Austin TX

International Business Machines Corporation - Armonk NY

G06F 300

395305

A system and method which utilizes a unique bus protocol in conjunctions plural Dval. sub. -- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval. sub. -- signals and data receivers look at all Dval. sub. -- signals and if any one of them is active, then the data is considered valid and can be read.

2004006, Apr 1, 2004

Sep 26, 2002

10/255975

Moinul Syed - Austin TX, US
Michael Allen - Austin TX, US

Analog Devices, Inc. - Norwood MA

G06F012/00

711/169000, 711/158000

A bus interface unit is provided for a digital signal processor including a core processor, a memory and two or more system buses for transfer of data to and from system components. The bus interface unit includes a first bus controller for receiving processor transfer requests from the core processor on two or more processor buses and for directing the processor transfer requests to the memory on a first memory bus. The bus interface further includes a second bus controller for receiving system transfer requests from the system components on the two or more system buses and for directing the system transfer requests to the memory on a second memory bus. The bus controllers may have pipelined architectures and may be configured to service transfer requests independently.

5782980, Jul 21, 1998

May 14, 1996

8/645619

Michael B. Allen - Austin TX
Dennis C. Swartz - Austin TX
Patrick B. Lee - Austin TX

Advanced Micro Devices, Inc.

C23C 1600

118715

A low-pressure CVD apparatus is presented including one or more gas heating subsystems which heat process gases prior to their introduction into a reaction chamber of the low-pressure CVD apparatus. As a result, thermal expansions and contractions of the walls of the reaction chamber are reduced, along with the tendency of small particles of deposits on the inner walls of the reaction chamber to flake off. Fewer loose particulates created within the reaction chamber results in a reduction in the number of particulates adhering to surfaces of processed silicon wafers. Each gas heating subsystem includes a heating element thermally coupled to a gas feed line and to a process gas flowing within the gas feed line. Each gas heating subsystem also preferably includes a thermal feedback temperature control mechanism including a temperature sensor and a temperature control unit. The temperature sensor senses the temperature of the heated flow of process gas and produces a corresponding temperature signal.

5771247, Jun 23, 1998

Mar 4, 1996

8/611439

Michael Scott Allen - Austin TX
Ravi Kumar Arimilli - Round Rock TX
John Michael Kaiser - Cedar Park TX
William Kurt Lewchuk - Austin TX

International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL

G06F 1110

371 401

A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr. sub. --) as a functional signal indicating a specific type of error in a particular system component. If the Derr. sub. -- signal is active, the parity error recognized by the CPU was caused by a correctable condition in a data providing device. In this instance, the processor will read the corrected data from a buffer without reissuing a fetch request. When the CPU finds a parity error, but Derr. sub. -- is not active a more serious fault condition is identified (bus error or uncorrectable multibit error) requiring a machine level interrupt, or the like. And, when no parity is found by the CPU and Derr. sub. -- is not active, then the data is known to be valid and the parity/ECC latency is eliminated, thereby saving processing cycle time.

5692218, Nov 25, 1997

Apr 25, 1996

8/639274

Michael Scott Allen - Austin TX
Michael Julio Garcia - Austin TX
Charles Roberts Moore - Austin TX
Robert James Reese - Austin TX

International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL

G06F 1300

395853

A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, an operation request package is transmitted to a second device from a first device, which informs the second device of the total amount of data to be transferred. A transfer signal is then transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device.

5745698, Apr 28, 1998

Aug 28, 1996

8/704035

Michael Scott Allen - Austin TX
Ravi Kumar Arimilli - Round Rock TX
John Michael Kaiser - Cedar Park TX
William Kurt Lewchuk - Austin TX

International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL

G06F 1516, G06F 1300

39520067

A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.

5659708, Aug 19, 1997

Oct 3, 1994

8/317256

Ravi Kumar Arimilli - Round Rock TX
John Michael Kaiser - Cedar Park TX
William Kurt Lewchuk - Austin TX
Michael Scott Allen - Austin TX

International Business Machines Corp. - Armonk NY

G06F 1208

395473

A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of another bus device. Unlike the modified response signal, this special signal is sent along with the requested data from the one bus device to the requesting bus device, indicating that this data has priority over any data being sent from the memory system coupled to the shared bus. The present invention allows for cache-to-cache and cache-to-memory-and-cache operations.

7043582, May 9, 2006

Sep 6, 2002

10/236856

Ravi P. Singh - Austin TX, US
Thomas Tomazin - Austin TX, US
Charles P. Roth - Austin TX, US
Jose Fridman - Swampscott MA, US
Michael Allen - Austin TX, US

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA

G06F 13/24

710260, 710264, 710266, 710261

A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.