MICHAEL KEITH FLOYD, M.D.
Urology at James Casey St, Austin, TX

8171319, May 1, 2012

Apr 16, 2009

12/425189

Soraya Ghiasi - Boulder CO, US
Malcolm S. Ware - Austin TX, US
Karthick Rajamani - Austin TX, US
Michael S. Floyd - Austin TX, US
Juan C. Rubio - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 1/32

713321, 713322, 713323

Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate. The voltage value, frequency value, and unique pointer of a given pstate definition are configurable, during operation of the data processing system, by the power manager module in response to changes in the operating parameters of the data processing system.

4807104, Feb 21, 1989

Apr 15, 1988

7/182010

Michael D. Floyd - Austin TX
Jeffrey D. Stump - Elgin TX

Motorola, Inc. - Schaumburg IL

H02M 318

363 59

A charge pump circuit and associated method is provided for outputting either a positive or a negative output voltage, or both, which each may have a predetermined magnitude which is an integer multiple of the magnitude of a power supply voltage used to power the circuit. In one form, a first capacitor is charged to the power supply voltage. The first capacitor is coupled to the power supply voltage to develop a double voltage transfer supply with the supply voltage. Second and third capacitors are charged by the double voltage transfer supply. The second capacitor is used to store the charge from the first capacitor for a continuous output voltage having a magnitude which is twice the magnitude of the power supply. The third capacitor may be reconfigured to generate a negative transfer voltage. The negative transfer voltage is used to charge a fourth capacitor which provides a negative output voltage with twice the magnitude of the power supply voltage.

2006018, Aug 17, 2006

Feb 11, 2005

11/055823

Michael Floyd - Austin TX, US
Larry Leitner - Austin TX, US
Sheldon Levenstein - Austin TX, US
Scott Swaney - Catskill NY, US
Brian Thompto - Austin TX, US

International Business Machines - Armonk NY

G06F 9/30

712218000

A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state and prevents instructions not checkpointed from checkpointing. After that, the method releases checkpointed state stores to a L2 cache, and drops stores not checkpointed. Next, the method blocks interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores selected registers from the current checkpointed state. Next, the method fetches instructions from restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions.

7080288, Jul 18, 2006

Apr 28, 2003

10/425423

Frank David Ferraiolo - Essex Junction VT, US
Michael Stephen Floyd - Austin TX, US
Robert James Reese - Austin TX, US
Kevin Franklin Reick - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 11/22

714 43, 714 56, 714700

A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

7657893, Feb 2, 2010

Apr 23, 2003

10/422025

William Joseph Armstrong - Rochester MN, US
Michael Stephen Floyd - Austin TX, US
Ronald Nick Kalla - Round Rock TX, US
Larry Scott Leitner - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 9/46, G06F 9/44

718104, 712229

An accounting method and multi-threaded processor include a mechanism for accounting for processor resource usage by threads within programs. Relative resource use is determined by detecting a particular cycle state of threads active within the processor. If instructions are dispatched for all threads or no threads, the processor cycle is accounted equally to all threads. Alternatively if no threads are in the particular cycle state, the accounting may be made using a prior state, or in conformity with ratios of the threads' priority levels. If only one thread is in the particular cycle state, that thread is accounted the entire processor cycle. If multiple threads are dispatching, but less than all threads are dispatching, the processor cycle is billed evenly across the dispatching threads.

7213169, May 1, 2007

Apr 3, 2003

10/406650

John Steven Dodson - Pflugerville TX, US
Michael Stephen Floyd - Austin TX, US
Jerry Don Lewis - Round Rock TX, US
Gary Alan Morrison - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714 30

An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written. The time stamp trace record includes a count of the number of address transactions that were not converted to trace records.

7418629, Aug 26, 2008

Feb 11, 2005

11/055870

Ra'ed Mohammad Al-Omari - Cedar Park TX, US
Michael Stephen Floyd - Austin TX, US
Paul Frank Lecocq - Cedar Park TX, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714 30

A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.

2006018, Aug 17, 2006

Feb 11, 2005

11/055801

Michael Floyd - Austin TX, US
Larry Leitner - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714045000

A trace array with added width is provided. Each trace array entry includes a data portion and a side counter portion. When a programmable subset of trace data repeats, a side counter is incremented. When the programmable subset of the trace data stops repeating, the trace data and the side counter value are stored in the trace array. The trace array may also include a larger counter. In this implementation, if the smaller side counter reaches its maximum value, a larger counter may begin counting. The larger counter value may then be stored in its own trace array entry instead of the trace data. A predetermined side counter value may mark the entry as a larger compression counter instead of as a data entry.

7657772, Feb 2, 2010

Feb 13, 2003

10/366437

Joachim Gerhard Clabes - Austin TX, US
Michael Stephen Floyd - Austin TX, US
Paul David Muench - Poughkeepsie NY, US
Lawrence Joseph Powell - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 1/04, G06F 1/14

713500, 713501, 713502, 327 83, 327138, 327512

An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

4962687, Oct 16, 1990

Sep 6, 1988

7/240538

Richard S. Belliveau - Austin TX
Michael R. Floyd - Austin TX
Steven E. Tulk - Austin TX

A63J 1700

84464R

The variable color lighting system includes a plurality of lamps controlled by a central controller. The central controller has a number of control channels, and each lamp is preset to be responsive to a specific control channel. To accomplish this, a lamp includes an address circuit which can be varied to respond to a unique address signal from any of the control channels. When the proper address is received, intensity control circuitry within the lamp responds to a digital intensity control signal transmitted by the central controller. The central controller causes all light sources in a lamp to fade from one end intensity value to the next and to reach the next intensity value simultaneously.