MICHAEL K. SMITH, PH.D.
Psychologist at Hamilton Ave, Palo Alto, CA

2009021, Aug 27, 2009

Feb 14, 2009

12/378328

Michael J.S. Smith - Palo Alto CA, US
Suresh Natarajan Rajan - San Jose CA, US
David T. Wang - San Jose CA, US

G06F 12/06

711105, 711E12083

One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

2013013, May 23, 2013

Sep 14, 2012

13/620424

Radoslav Danilak - Cupertino CA, US
Michael J.S. Smith - Palo Alto CA, US
Suresh Rajan - San Jose CA, US

GOOGLE, INC. - Mountain View CA

G06F 3/06

711103

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

5274825, Dec 28, 1993

Oct 30, 1992

7/969551

Richard A. Lemay - Carlisle MA
Michael D. Smith - Palo Alto CA

Bull HN Information Systems Inc. - Billerica MA

G06F 1300

395725

A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.

2004006, Apr 1, 2004

Jun 5, 2003

10/456871

John Minami - Honolulu HI, US
Robin Uyeshiro - Kailua HI, US
Michael Johnson - Livermore CA, US
Steve Su - Honolulu HI, US
Michael Smith - Palo Alto CA, US
Addison Chen - Honolulu HI, US
Mihir Doctor - Honolulu HI, US
Daniel Greenfield - Honolulu HI, US

H04L012/66

370/463000

The invention is embodied in a gigabit Ethernet adapter. A system according to the invention provides a compact hardware solution to handling high network communication speeds. In addition, the invention adapts to multiple communication protocols via a modular construction and design.

2012012, May 17, 2012

Oct 18, 2011

13/276212

Radoslav Danilak - Cupertino CA, US
Michael J.S. Smith - Palo Alto CA, US
Suresh Rajan - San Jose CA, US

Google, Inc. - Mountain View CA

G06F 12/02

711103, 711E12008

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

2013010, Apr 25, 2013

Sep 14, 2012

13/620425

Suresh N. Rajan - San Jose CA, US
Keith R. Schakel - San Jose CA, US
Michael J.S. Smith - Palo Alto CA, US
David T. Wang - Thousand Oaks CA, US
Frederick Daniel Weber - San Jose CA, US

GOOGLE INC. - Mountain View CA

G06F 12/00

711105

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

2008008, Apr 10, 2008

Dec 15, 2006

11/611374

Radoslav Danilak - Cupertino CA, US
Michael J.S. Smith - Palo Alto CA, US
Suresh Rajan - San Jose CA, US

G06F 12/00

711103

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.