Inventors:
Michael J. Redig - Loveland CO
David M. Prater - Loveland CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G05B 1902, H03D 324, H03L 700, H03L 708
Abstract:
A device for synchronizing the output test pattern signals of a test circuit with the clock signal of a device under test (DUT). The invention uses a programmable delay in the feedback loop of a phase locked loop system to adjust the phase of the test pattern signals to be synchronized with the clock of the device under test (DUT).