MICHAEL ANTHONY SCHROEDER
Pilots at Figtree Ln, Plano, TX
License number
Texas A4703692
Issued Date
Jun 2015
Expiration Date
Jun 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
2608 Figtree Ln, Plano, TX 75074
Professional information
Non-Inclusive Cache Systems And Methods
US Patent:
2008025, Oct 16, 2008
Filed:
Apr 11, 2007
Appl. No.:
11/733857
Inventors:
Craig Warner - Addison TX, US
Dan Robinson - Allen TX, US
John Wastlick - Allen TX, US
Michael Schroeder - Plano TX, US
Dan Robinson - Allen TX, US
John Wastlick - Allen TX, US
Michael Schroeder - Plano TX, US
International Classification:
G06F 12/16
US Classification:
711152
Abstract:
Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.
Circuitry And Method To Detect Conditions Of Data
US Patent:
7774652, Aug 10, 2010
Filed:
Sep 19, 2006
Appl. No.:
11/523472
Inventors:
Richard Adkisson - Plano TX, US
Michael Schroeder - Plano TX, US
Michael Schroeder - Plano TX, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G01R 31/3177
US Classification:
714 37, 714812
Abstract:
A system may comprise a condition detection system that includes change circuitry configured to detect a change for at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition. Match circuitry is configured to detect a match condition for up to a selected subset of predetermined bits of the N-bit bus and to provide a corresponding match signal indicative of the detected condition. Selection circuitry is programmable to provide a selected one of the change signal and the match signal as a corresponding output signal.
Systems And Methods For Mitigating Latency Associated With Error Detection And Correction
US Patent:
7577890, Aug 18, 2009
Filed:
Jan 21, 2005
Appl. No.:
11/040380
Inventors:
Michael A. Schroeder - Plano TX, US
Christopher Michael Brueggen - Allen TX, US
Gary B. Gostin - Plano TX, US
Christopher Michael Brueggen - Allen TX, US
Gary B. Gostin - Plano TX, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H04L 1/18
US Classification:
714748, 714776, 714758, 714799
Abstract:
Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.