MR. LE MINH QUACH, B.S./R.D.H.
Dental Hygienist at Berryessa Rd, San Jose, CA
License number
California 22109
Category
Dental Hygienist
Type
Dental Hygienist
Address
Address
2664 Berryessa Rd SUITE 210, San Jose, CA 95132
Phone
(408) 431-6975
(408) 258-8838 (Fax)
(408) 258-8838 (Fax)
Personal information
See more information about LE MINH QUACH at radaris.comName
Address
Phone
Sacramento, CA
517 Florence Ave, Monterey Park, CA 91755
9122 Oasis Ave, Westminster, CA 92683
425 Orange Ave, Monterey Park, CA 91755
36 Tesoro, Mission Viejo, CA 92692
Professional information
Automatic Delay Element Insertion System For Addressing Holdtime Problems
US Patent:
6546531, Apr 8, 2003
Filed:
Oct 6, 2000
Appl. No.:
09/684284
Inventors:
Le Quach - San Jose CA
Lakshminarasimhan Varadadesikan - Santa Clara CA
Dale R. Greenley - Los Gatos CA
Lakshminarasimhan Varadadesikan - Santa Clara CA
Dale R. Greenley - Los Gatos CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 945
US Classification:
716 6, 716 5, 716 4
Abstract:
Hold time methods, systems, and computer program products are implemented to ensure that storage elements in a circuit have sufficient hold times without detrimentally affecting cycle times for other paths in the circuit. Electric circuits are designed by determining which storage elements have hold-time deficiencies, and by inserting an appropriate time delay element in a selected path preceding the storage element, or at a source or destination storage element, without exceeding a predetermined cycle time in a second path that overlaps the first path, for at least one storage element in an electrical circuit. The invention simulates insertion of the time delay element before or after a logic element that precedes a storage element that has a hold-time deficiency. The invention determines which storage elements and which circuit paths between adjacent storage elements are subject to hold time deficiencies, assembles a hold time deficiency list, and determines whether a selected hold-time-deficient storage element can be preceded with a delay element without violating a cycle time constraint in another cycle path. The invention further includes determining the placement of a delay element in a storage system having a network of storage elements interconnected with logic elements by using a criterion that protects cycle times in other storage element paths with slower signal propagation.
Method For Selectively Implementing Low Threshold Voltage Transistors In Digital Logic Designs
US Patent:
8627252, Jan 7, 2014
Filed:
Sep 18, 2008
Appl. No.:
12/233191
Inventors:
Le Tu Quach - San Jose CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 17/50
US Classification:
716113, 716104, 716126
Abstract:
A system and method for selectively replacing standard threshold voltage devices with low threshold voltage devices in a digital logic design. The system identifies at least one path having a first timing value, the path having a plurality of standard threshold devices. The path is reverse traversed, or otherwise analyzed or traversed, to identify at least one of the standard threshold devices to possibly replace with a corresponding low threshold device. The system also determines a timing value for the path associated with replacing the at least one standard threshold device with the corresponding low threshold device. Depending the analysis, the standard threshold device may be replaced with a low threshold device, such as when the path timing improves by replacement. Such replacement may be used in various paths, such as paths considered critical paths in a digital logic design.