Kenneth James Jones
Physician at Medical Pkwy, Austin, TX

2014001, Jan 16, 2014

Sep 18, 2013

14/029989

Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US

Apple Inc. - Cupertino CA

G11C 5/06

365 72

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

5473561, Dec 5, 1995

Sep 15, 1994

8/306565

Kenneth W. Jones - Austin TX
Mark D. Bader - Austin TX
Ketan B. Shah - Round Rock TX

Motorola Inc. - Schaumburg IL

G11C 1500

365 49

A cache TAG RAM (25) includes a reduction circuit (39) for comparing match signals from a plurality of exclusive OR logic circuits (33, 34) and provides a hit signal when all of the TAG address bits of a stored TAG address is the same as input address bits. The reduction circuit (39) provides a miss signal when any one or more of the bits of the stored TAG address is not the same as the corresponding bits of the input address bits. In one embodiment, the reduction circuit (39) uses a plurality of transistors (77, 78) coupled to a conductor (75) for discharging the conductor (75) if one of the exclusive OR logic circuits (33, 34) indicates a miss. In another embodiment, the reduction circuit (39") charges the conductor. The comparison can be made using signals having small signal swing at high speed, and a reference voltage is not needed for the comparison.

5477176, Dec 19, 1995

Jun 2, 1994

8/253076

Ray Chang - Austin TX
Lawrence F. Childs - Austin TX
Kenneth W. Jones - Austin TX
Donovan Raatz - Austin TX
Stephen Flannagan - Austin TX

Motorola Inc. - Schaumburg IL

H03L 700

327143

A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N. sub. BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

5802586, Sep 1, 1998

Feb 27, 1995

8/395225

Kenneth W. Jones - Austin TX
Mark D. Bader - Austin TX
Arthur D. Kahlich - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1200

711155

A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write operation. This is accomplished by using a write column logic (47) and a read column logic (51) to delay write column decode signals by one clock cycle from the read column decode signals. When data is being burst into and out of the cache during the read-modify-write operation, the first read cycle from the cache array (40) occurs, and one clock cycle later, the first write cycle occurs. The first write cycle occurs during the same time interval as the second read cycle. This increases the speed of a read-modify-write operation, relaxes timing constraints on the read and write operations, while reducing the power consumption of the cache.

5268863, Dec 7, 1993

Jul 6, 1992

7/909485

Mark D. Bader - Austin TX
Kenneth W. Jones - Austin TX
Karl L. Wang - Austin TX
Ray Chang - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 700

36518901

A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

5485110, Jan 16, 1996

Feb 1, 1994

8/189776

Kenneth W. Jones - Austin TX
Stephen T. Flannagan - Austin TX

Motorola Inc. - Schaumburg IL

H03K 19086, H03K 1762

327 99

An ECL multiplexing circuit (20) includes two differential pairs (21 and 22) for receiving first and second ECL level input signals, emitter-follower output transistors (27 and 28), and a differential pair (31 and 32) for receiving differential clock signals. The differential clock signals control which of the two differential pairs (21 and 22) is coupled to the emitter-follower output transistors (27 and 28). The ECL level input signals that control a logic state of the output signals is determined by the logic state of the clock signals. The ECL multiplexing circuit (20) receives non-overlapping clock signals and is used in a quadrature frequency divide-by-two circuit (40) to divide a frequency of an input clock signal by two.

8553472, Oct 8, 2013

Dec 5, 2011

13/311340

Edward M. McCombs - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US

Apple Inc. - Cupertino CA

G11C 7/10

36518905, 365226, 365229, 365227, 36523008

A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.