Inventors:
Jerald R. Bernacchi - Los Altos CA
Graham Y. Mostyn - Saratoga CA
Mohammad Yunus - Fremont CA
International Classification:
H03K 19003
Abstract:
A circuit and method for avoiding latch up in an integrated circuit in which the base-emitter junction of a parasitic bipolar transistor forming part of a parasitic SCR structure is monitored. If the forward bias of the monitored base-emitter junction approaches a predetermined value, the operation of the circuit is altered to prevent activation of the SCR.