DR. FRED SHOONG-PING CHEN, M.D.
Student, Health Care in San Francisco, CA
License number
California A100761
Category
Student, Health Care
Type
Student in an Organized Health Care Education/Training Program
Address
Address
505 Parnassus Ave Department Of Radiology, San Francisco, CA 94143
Phone
(415) 476-8358
(415) 476-0616 (Fax)
(858) 405-9773
(415) 476-0616 (Fax)
(858) 405-9773
Personal information
See more information about FRED SHOONG-PING CHEN at radaris.comName
Address
Phone
10341 Beach Blvd, Stanton, CA 90680
504 W Huntington Dr UNIT 11, Arcadia, CA 91007
606 Shadowhawk Way, Walnut Creek, CA 94595
618 S 6Th St APT A, Alhambra, CA 91801
622 Bucher Ave, Santa Clara, CA 95051
Professional information
Methods And Circuits For Performing Margining Tests In The Presence Of A Decision Feedback Equalizer
US Patent:
7408981, Aug 5, 2008
Filed:
May 20, 2003
Appl. No.:
10/441461
Inventors:
Fred F. Chen - San Francisco CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03H 7/30, H04L 27/00
US Classification:
375229, 375316
Abstract:
Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i. e. , the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.
Ram-Dac For Transmit Preemphasis
US Patent:
2007002, Feb 1, 2007
Filed:
Jul 29, 2005
Appl. No.:
11/193916
Inventors:
Andrew Ho - Palo Alto CA, US
Fred Chen - San Francisco CA, US
Jared Zerbe - Woodside CA, US
Fred Chen - San Francisco CA, US
Jared Zerbe - Woodside CA, US
International Classification:
H04L 7/00
US Classification:
375372000
Abstract:
Described are transmitters with RAM-DAC based pre-emphasis filters that can be updated adaptively without interfering with data transmission. The memory within the RAM-DAC is divided into active and inactive memory locations, in which active memory locations are those to be accessed in the near future, and consequently cannot be updated (written to) at a given time due without inducing a read/write conflict. One embodiment monitors incoming memory addresses to find an adequate time window for a write to take place without a read interference. Another embodiment includes two memory blocks with similar address space, one of which may be updated as the other is used to for data transmission. Some embodiments employ a RAM-DAC with reduced memory size and complexity.
Selectable-Tap Equalizer
US Patent:
8467437, Jun 18, 2013
Filed:
Nov 12, 2008
Appl. No.:
12/269488
Inventors:
Jared L Zerbe - Woodside CA, US
Vladimir M Stojanovic - Stanford CA, US
Fred F Chen - San Francisco CA, US
Vladimir M Stojanovic - Stanford CA, US
Fred F Chen - San Francisco CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H03H 7/30, H03H 7/40, H03K 5/159
US Classification:
375229, 375232, 375350
Abstract:
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
Transparent Multi-Mode Pam Interface
US Patent:
7308058, Dec 11, 2007
Filed:
Mar 19, 2004
Appl. No.:
10/805413
Inventors:
Jared L. Zerbe - Woodside CA, US
Carl W. Werner - Los Gatos CA, US
William F. Stonecypher - San Jose CA, US
Fred F. Chen - San Francisco CA, US
Carl W. Werner - Los Gatos CA, US
William F. Stonecypher - San Jose CA, US
Fred F. Chen - San Francisco CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03K 9/02
US Classification:
375353, 375286, 375259
Abstract:
Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.
Equalizing Transceiver With Reduced Parasitic Capacitance
US Patent:
6982587, Jan 3, 2006
Filed:
Oct 1, 2002
Appl. No.:
10/261875
Inventors:
Fred F. Chen - San Francisco CA, US
Vladimir M. Stojanovic - Stanford CA, US
Vladimir M. Stojanovic - Stanford CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06G 7/12
US Classification:
327355, 327361, 327352, 326 30
Abstract:
A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.
Selectable-Tap Equalizer
US Patent:
7860156, Dec 28, 2010
Filed:
Apr 2, 2009
Appl. No.:
12/417263
Inventors:
Jared L Zerbe - Woodside CA, US
Vladimir M Stojanovic - Stanford CA, US
Fred F Chen - San Francisco CA, US
Vladimir M Stojanovic - Stanford CA, US
Fred F Chen - San Francisco CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H03H 7/30, H03H 7/40, H03K 5/159
US Classification:
375229, 375231, 375232, 375346, 375350
Abstract:
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
Signaling System With Data Correlation Detection
US Patent:
2007004, Mar 1, 2007
Filed:
Aug 24, 2005
Appl. No.:
11/211351
Inventors:
Vladimir Stojanovic - Lexington MA, US
Andrew Ho - Palo Alto CA, US
Fred Chen - San Francisco CA, US
Simon Li - Sunnyvale CA, US
Andrew Ho - Palo Alto CA, US
Fred Chen - San Francisco CA, US
Simon Li - Sunnyvale CA, US
International Classification:
H03H 7/30, H04L 27/06
US Classification:
375229000, 375343000
Abstract:
Conditionally updating equalization tap weights within an equalized signaling system based on a measure of correlation that indicates a difference between the number of received data values that have matching bits at a first pair of predetermined bit positions, and the number of received data values that have non-matching bits at the first pair of predetermined bit positions.
Selectable-Tap Equalizer
US Patent:
8472511, Jun 25, 2013
Filed:
Dec 13, 2011
Appl. No.:
13/324783
Inventors:
Jared L. Zerbe - Woodside CA, US
Vladimir M. Stojanovic - Stanford CA, US
Fred F. Chen - San Francisco CA, US
Vladimir M. Stojanovic - Stanford CA, US
Fred F. Chen - San Francisco CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H03H 7/40
US Classification:
375232
Abstract:
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
Equalizing Transceiver With Reduced Parasitic Capacitance
US Patent:
7348811, Mar 25, 2008
Filed:
Oct 14, 2005
Appl. No.:
11/251139
Inventors:
Fred F. Chen - San Francisco CA, US
Vladimir M. Stojanovic - Stanford CA, US
Vladimir M. Stojanovic - Stanford CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H03K 3/10
US Classification:
327112, 327108, 327109, 327110, 327111, 326 26, 326 27, 326 30, 326 82, 326 83, 326 85, 326 86, 326 87, 326 91
Abstract:
A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.
Selectable-Tap Equalizer
US Patent:
7873115, Jan 18, 2011
Filed:
Nov 12, 2008
Appl. No.:
12/269532
Inventors:
Jared L Zerbe - Woodside CA, US
Vladimir M Stojanovic - Stanford CA, US
Fred F Chen - San Francisco CA, US
Vladimir M Stojanovic - Stanford CA, US
Fred F Chen - San Francisco CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H04B 15/00
US Classification:
375285, 375229, 375232, 375346, 375348
Abstract:
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.