DOUGLAS RAY ANDERSON
Pilots in Vancouver, WA

License number
Washington A0035368
Issued Date
Jun 2016
Expiration Date
Jun 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
PO Box 5806, Vancouver, WA 98668

Professional information

Douglas Anderson Photo 1

Wafer, Intermediate Wafer Assembly And Associated Method For Fabricating A Silicon On Insulator Wafer Having An Improved Edge Profile

US Patent:
2005016, Jul 28, 2005
Filed:
Jan 22, 2004
Appl. No.:
10/762789
Inventors:
Douglas Anderson - Vancouver WA, US
International Classification:
H01L023/04, H01L021/30
US Classification:
257730000, 438459000
Abstract:
A wafer, an intermediate wafer assembly and an improved method of fabricating a wafer having an improved edge profile are provided. The wafer may have various edge profiles that eliminate, or at least reduce, the chamfered portion proximate one of the major surfaces. For example, the wafer may have an edge with curved surface extending continuously from one major surface to another, an angled edge segment adjacent one major surface and a curved surface extending from the angled edge segment to the other major surface, or first and second angled edge segments adjacent the opposed major surfaces and a curved surface extending therebetween with the second angled edge segment being at least 50% smaller in a radial direction than the first angled edge segment. The wafer may serve as the bonded wafer, the handle wafer, or both the bonded and handle wafers of an SOI wafer.


Douglas Anderson Photo 2

Method For Evaluating Impurity Concentrations In Heat Treatment Furnaces

US Patent:
6423556, Jul 23, 2002
Filed:
Nov 14, 2001
Appl. No.:
10/003994
Inventors:
Sergei V. Koveshnikov - Vancouver WA
Douglas G. Anderson - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
H01L 2166
US Classification:
438 14, 438476, 438471, 438928, 438974
Abstract:
A method for evaluating the concentration of impurities in gases and equipment used in heat treatment of a semiconductor substrate is provided. The method includes processing a semiconductor substrate of known impurity levels in a heat treatment furnace, and measuring the impurity levels after the heat treatment processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the heat treatment process.


Douglas Anderson Photo 3

Methods Of Producing Doped Semiconductors

US Patent:
6350315, Feb 26, 2002
Filed:
Dec 22, 2000
Appl. No.:
09/747820
Inventors:
Douglas G. Anderson - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
C30B 904
US Classification:
117 20, 117 2, 117 3, 117 9
Abstract:
Methods for producing doped polycrystalline semiconductors and for producing doped monocrystalline semiconductors from predoped monocrystalline and polycrystalline semiconductors. The methods for producing doped polycrystalline semiconductors may include (1) providing a reactor for chemical vapor deposition, (2) creating a vapor within the reactor that includes a silicon compound and a preselected dopant, and (3) providing a substrate, exposed to the vapor, onto which the silicon and the dopant in the vapor are deposited to form doped polycrystalline silicon. The methods for producing doped monocrystalline semiconductors may include (1) selecting a first amount of a first semiconductor, the first semiconductor having a first concentration of the dopant, (2) selecting a second amount of a second semiconductor, and (3) using the first and second amounts to grow a monocrystalline semiconductor having a preselected concentration of the dopant.


Douglas Anderson Photo 4

Method For Evaluating Impurity Concentrations In Unpolished Wafers Grown By The Czochralski Method

US Patent:
6630363, Oct 7, 2003
Filed:
Nov 14, 2001
Appl. No.:
10/004065
Inventors:
Sergei V. Koveshnikov - Vancouver WA
Douglas G. Anderson - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
H01L 2166
US Classification:
438 14, 438 16, 438471, 438476
Abstract:
A method for evaluating the concentration of impurities in as-grown monocrystalline semiconductor ingots is provided. The method includes growing a monocrystalline semiconductor ingot, and measuring the bulk impurity levels of the ingot by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of a sample of the monocrystalline semiconductor ingot to getter impurities from the sample into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were grown into the monocrystalline semiconductor ingot.


Douglas Anderson Photo 5

Method For Evaluating Impurity Concentrations In Epitaxial Susceptors

US Patent:
6649427, Nov 18, 2003
Filed:
Nov 14, 2001
Appl. No.:
10/003960
Inventors:
Sergei V. Koveshnikov - Vancouver WA
Douglas G. Anderson - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
H01L 2166
US Classification:
438 14, 438 16, 438471, 438476, 438142FOR
Abstract:
A method for non-destructively evaluating the concentration of impurities in an epitaxial susceptor used in the processing of a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels on the epitaxial susceptor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.


Douglas Anderson Photo 6

Melt Spill Indicator Device

US Patent:
6348870, Feb 19, 2002
Filed:
Dec 28, 2000
Appl. No.:
09/753061
Inventors:
Douglas G. Anderson - Vancouver WA
Richard M. Aydelott - Ridgefield WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
G08B 2100
US Classification:
340605, 340604, 340584, 340593, 117 11
Abstract:
An apparatus for determining a melt spill during Czochralski crystal growing processes, having a sensor or detector that allows the creation or cessation of a signal when the presence of melt spill is detected. This invention includes a sensor or detector that can operate in high temperature conditions without causing contamination to the crystal growth process. Any detected melt spill triggers an alarm so that potentially dangerous and costly situations may be avoided. The melt spill detector may be placed in any location advantageous to detect the melt spill, and may be incorporated into the components of the crystal growing apparatus.


Douglas Anderson Photo 7

Methods Of Producing Doped Semiconductors

US Patent:
6171389, Jan 9, 2001
Filed:
Sep 30, 1998
Appl. No.:
9/163858
Inventors:
Douglas G. Anderson - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
C30B 904
US Classification:
117 2
Abstract:
Methods for producing doped polycrystalline semiconductors and for producing doped monocrystalline semiconductors from predoped monocrystalline and polycrystalline semiconductors. The methods for producing doped polycrystalline semiconductors may include (1) providing a reactor for chemical vapor deposition, (2) creating a vapor within the reactor that includes a silicon compound and a preselected dopant, and (3) providing a substrate, exposed to the vapor, onto which the silicon and the dopant in the vapor are deposited to form doped polycrystalline silicon. The methods for producing doped monocrystalline semiconductors may include (1) selecting a first amount of a first semiconductor, the first semiconductor having a first concentration of the dopant, (2) selecting a second amount of a second semiconductor, and (3) using the first and second amounts to grow a monocrystalline semiconductor having a preselected concentration of the dopant.


Douglas Anderson Photo 8

Gauge Block Holder Apparatus

US Patent:
6014886, Jan 18, 2000
Filed:
Jun 30, 1998
Appl. No.:
9/107017
Inventors:
Douglas G. Anderson - Vancouver WA
Jason D. Jordan - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
G01B 506
US Classification:
73 181
Abstract:
A gauge block holder that greatly reduces measurement error in calibrating wafer thickness test equipment is described. In a preferred embodiment of the invention, the gauge block holder is compatible with present thickness measurement equipment and provides a central region specially configured for holding a prior art gauge block in a manner that ensures precise, parallel alignment thereof with the equipment and thus precise perpendicular alignment with the equipment's opposing contact pins. Preferably a gauge block-sized and shaped recess and aperture are provided centrally in the holder such that the gauge block rests immobile on and parallel with the precision-machined, planar upper surface of a metal plate of the thickness tester while the thickness tester is being calibrated for a given wafer thickness measurement. The recess and aperture in accordance with their preferred embodiment are rectangular, and the invented gauge block preferably is securely fastened to the metal plate, e. g. with screws, although alternative configurations and fasteners are contemplated for accurate, repeatable calibration with alternative gauge blocks.


Douglas Anderson Photo 9

Combination Wafer Carrier And Storage Device

US Patent:
5657879, Aug 19, 1997
Filed:
Feb 5, 1996
Appl. No.:
8/596956
Inventors:
Douglas G. Anderson - Vancouver WA
Jason D. Jordan - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
A47F 700
US Classification:
211 4118
Abstract:
A combination wafer carrier and basket-like storage device that includes insertable and removable plates for adjustment of capacity, as well as insertable and removable basket-like sleeves for adaptation to various-sized wafers.