DOUGLAS LYLE GABEL
Pilots at Bagley Rd, Beaverton, OR

8253751, Aug 28, 2012

Jun 30, 2005

11/173375

Peter MacWilliams - Aloha OR, US
James Akiyama - Beaverton OR, US
Douglas Gabel - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 13/28

345533, 345544, 345564

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

7558941, Jul 7, 2009

Jun 30, 2005

11/172766

Douglas Gabel - Hillsboro OR, US
James Akiyama - Beaverton OR, US

Intel Corporation - Santa Clara CA

G06F 9/26, G06F 9/34, G11C 29/00, G01R 31/28

711217, 714719, 714735

In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory accesses into each memory integrated circuit on memory modules in the memory channel. A read cache line is read from memory in the memory channel at the starting address. The bit patterns of the read cache line and the write cache line are compared. If in the comparison it is determined that the bit pattern of the read cache line differs from the write cache line, then micro-tile memory access is enabled into each memory integrated circuit on memory modules in the memory channel. If in the comparison it is determined that the bit pattern of the read cache line is the same as the bit pattern of the write cache line, then micro-tile memory access is not supported and cannot be enabled in each memory integrated circuit on memory modules in the memory channel.

5930504, Jul 27, 1999

Jul 22, 1996

8/686170

Douglas L. Gabel - Hillsboro OR

Intel Corporation - Santa Clara CA

G06F 906

395652

An improved process for updating a nonvolatile memory of a computer system includes selecting a logical area of the nonvolatile memory to update. Protected procedures are copied from one of the selected logical area and an update file. Information from the update file is copied to the nonvolatile memory in accordance with the copied protected procedures. Another method of updating the nonvolatile memory includes selecting at least a portion of the nonvolatile memory to update. Protected procedures including an updated memory map are copied from an update file. Information from the update file is copied to the nonvolatile memory in accordance with the copied protected procedures. An update file to facilitate the improved update processes includes a header section and a update information section. The update information section includes updated code and data for the nonvolatile memory. The header includes a code usage indicator, and offsets to an update table and protected procedures in order to facilitate the update process.

5579522, Nov 26, 1996

Jul 24, 1995

8/505995

Orville H. Christeson - Portland OR
Douglas L. Gabel - Aloha OR
Sean T. Murphy - Portland OR

Intel Corporation - Santa Clara CA

G06F 906

395652

A computer system wherein a portion of code/data stored in a non-volatile memory device can be dynamically modified or updated without removing any covers or parts from the computer system. The computer system of the preferred embodiment includes a flash memory component coupled to a computer system bus for storing non-volatile code and data. Using the present invention, the contents of a portion of the flash memory may be replaced, modified, updated, or reprogrammed without the need for removing and/or replacing any computer system hardware components. The flash memory device used in the preferred embodiment contains four separately erasable/programmable non-symmetrical blocks of memory. One of these four blocks may be electronically locked to prevent erasure or modification of its contents once it is installed. This configuration allows the processing logic of the computer system to update or modify any selected block of memory without affecting the contents of other blocks.

5479639, Dec 26, 1995

Aug 26, 1994

8/279692

James H. Ewertz - Portland OR
Orville H. Christeson - Portland OR
Douglas L. Gabel - Aloha OR
Sean T. Murphy - Portland OR

Intel Corporation - Santa Clara CA

G06F 1202

395430

A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Using the apparatus and techniques of the present invention, Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages, Page 1, Page 3, and Page 4, contain processing logic called swapping logic used during the swapping or paging operation.

2009006, Mar 12, 2009

Sep 11, 2007

11/853149

DOUGLAS GABEL - Hillsboro OR, US
DAVID HARRIMAN - Portland OR, US

G06F 17/00

700 94

Embodiments of the invention are generally directed to systems, methods, and apparatuses for encapsulation of high definition audio data over an input/output interconnect. In some embodiments, a system includes tunneling logic coupled with a high definition (HD) audio controller. The tunneling logic may receive digital audio data from the HD audio controller, encapsulate the digital audio data in a message suitable for an in-band input/output (IO) interconnect, and send the message to an add-in graphics card via the in-band input/output IO interconnect. Other embodiments are described and claimed.

8310854, Nov 13, 2012

Sep 30, 2011

13/250386

Peter MacWilliams - Aloha OR, US
James Akiyama - Beaverton OR, US
Kuljit S. Bains - Olympia WA, US
Douglas Gabel - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G11C 11/00, G11C 7/00, G11C 8/00, G06F 13/00

365 52, 36518912, 365226, 36523003, 36523005, 3651331, 36523313, 365236, 365240, 711119, 711122

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

8200883, Jun 12, 2012

May 24, 2011

13/114903

Peter MacWilliams - Aloha OR, US
James Akiyama - Beaverton OR, US
Douglas Gabel - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 12/00

711 5, 711 4, 711100, 711102, 711103, 711104, 711105, 711106, 36523001, 36523002, 36523003, 36523005, 365 491, 365189011, 36518902, 36518904, 36518914, 36518919, 710 36, 710 37, 710 38, 710 39, 710 40

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

8064237, Nov 22, 2011

Dec 21, 2010

12/974862

Peter MacWilliams - Aloha OR, US
James Akiyama - Beaverton OR, US
Kuljit S. Bains - Olympia WA, US
Douglas Gabel - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G11C 5/00, G11C 7/00, G11C 8/00

365 52, 36518912, 365201, 36523003, 3652331, 36523313, 365236, 365240, 710 22, 710122

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

2009017, Jul 2, 2009

Dec 31, 2007

11/967988

Douglas Gabel - Hillsboro OR, US
Moshe Maor - Haifa, IL

INTEL CORPORATION - Santa Clara CA

H04L 9/32

713168

In some embodiments input information received at an input device is encrypted before it is sent to a computer to be coupled to the input device. Other embodiments are described and claimed.