JOHN BENTLEY HALBERT, III
Pilots at Marseilles Dr, Beaverton, OR

6493250, Dec 10, 2002

Dec 28, 2000

09/753024

John B. Halbert - Beaverton OR
James M. Dodd - Shingle Springs CA
Chung Lam - Redwood City CA
Randy M. Bonella - Portland OR

Intel Corporation - Santa Clara CA

G11C 506

365 63, 365 51, 365 52, 36523003

Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

6785190, Aug 31, 2004

May 20, 2003

10/442335

Kuljit S. Bains - Olympia WA
John Halbert - Beaverton OR

Intel Corporation - Santa Clara CA

G11C 800

365235, 36523003

An efficient invention for opening two pages of memory for a DRAM are discussed.

8238189, Aug 7, 2012

Apr 28, 2011

13/096137

Kuljit S. Bains - Olympia WA, US
John Halbert - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 8/00

36523003, 365193, 36523001

Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

7353329, Apr 1, 2008

Sep 29, 2003

10/674981

Robert M. Ellis - Hillsboro OR, US
Kuljit S. Bains - Olympia WA, US
Chris B. Freeman - Portland OR, US
John B. Halbert - Beaverton OR, US
Narendra S. Khandekar - Folsom CA, US
Michael W. Williams - Citrus Heights CA, US

Intel Corporation - Santa Clara CA

G06F 12/16

711106, 365222, 365228

Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

2013011, May 9, 2013

Sep 14, 2012

13/619452

Kuljit S. Bains - Olympia WA, US
David J. Zimmerman - El Dorado Hills CA, US
Dennis W. Brzezinski - Sunnyvale CA, US
Michael Williams - Folsom CA, US
John B. Halbert - Beaverton OR, US

G06F 11/10

714802

A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

2011013, Jun 9, 2011

Dec 9, 2009

12/634286

KULJIT S. BAINS - OLYMPIA WA, US
DAVID J. ZIMMERMAN - EL DORADO HILLS CA, US
DENNIS W. BRZEZINSKI - SUNNYVALE CA, US
MICHAEL WILLIAMS - FOLSOM CA, US
JOHN B. HALBERT - BEAVERTON OR, US

H03M 13/09, G06F 11/10

714800, 714807, 714E11032

A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

7050351, May 23, 2006

Dec 30, 2003

10/750038

John B. Halbert - Beaverton OR, US
Robert M. Ellis - Hillsboro OR, US
Kuljit S. Bains - Olympia WA, US
Chris B. Freeman - Portland OR, US

Intel Corporation - Santa Clara CA

G11C 8/00

36523003, 36523008

Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.

8289797, Oct 16, 2012

Oct 31, 2007

11/932470

Sandeep K Jain - Milpitas CA, US
Animesh Mishra - Pleasanton CA, US
John B Halbert - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 11/406

365222, 711105, 711106, 365149

A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

7386765, Jun 10, 2008

Sep 29, 2003

10/674320

Robert M. Ellis - Hillsboro OR, US
Kuljit S. Bains - Olympia WA, US
Chris B. Freeman - Portland OR, US
John B. Halbert - Beaverton OR, US

Intel Corporation - Santa Clara CA

G06F 11/00, G06F 3/00, G06F 12/00

714 62, 714 6, 710 52, 711100

Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

2013027, Oct 17, 2013

Dec 2, 2011

13/997148

Pete Vogt - Boulder CO, US
Andre Schaefer - Braunschweig, DE
Warren Morrow - Steilacoom WA, US
John Halbert - Beaverton OR, US
Jin Kim - Beaverton OR, US
Kenneth Shoemaker - Los Altos Hills CA, US

INTEL CORPORATION - Santa Clara CA

G11C 5/06, H01L 23/48

365 63, 257774

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.