DAVID SCOTT YOUNG
Pilots at Willow Gln Way, San Jose, CA
License number
California A2481580
Issued Date
Jun 2015
Expiration Date
Jun 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
1196 Willow Glen Way, San Jose, CA 95125
Professional information
David Young
Specialties:
Art History
Work:
Evergreen Valley College
Precoded Waveshaping Transmitter For A Twisted Pair Which Eliminates The Need For A Filter
US Patent:
5995555, Nov 30, 1999
Filed:
Oct 9, 1997
Appl. No.:
8/947924
Inventors:
David Young - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04L 2503
US Classification:
375296
Abstract:
A precoded waveshaping transmitter comprises a synchronous delay line circuit, a transmitter state machine and a differential current digital to analog converter. Through the provision of a plurality of precoded staggered time delayed data from the combination of the delay line circuit and transmitter state machine the DAC can provide a predetermined output. In a preferred implementation, a subharmonic frequency can be maintained at least 27dB below the fundamental frequency when the PWT is driven by an all ones Manchester encoded signal.
Precise Delay Line Circuit With Predetermined Reset Time Limit
US Patent:
5539348, Jul 23, 1996
Filed:
Mar 17, 1994
Appl. No.:
8/214897
Inventors:
David Young - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03H 1126
US Classification:
327262
Abstract:
A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.
Precise Delay Line Circuit With Predetermined Reset Time Limit
US Patent:
5801568, Sep 1, 1998
Filed:
Dec 6, 1995
Appl. No.:
8/567979
Inventors:
David Young - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03H 1126
US Classification:
327284
Abstract:
A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.