DAVID NICHOLS WALTER
Pilots at Tamaron Ct, Dallas, TX
License number
Texas A4227673
Issued Date
Jul 2016
Expiration Date
Jul 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
5531 Tamaron Ct, Dallas, TX 75287
Professional information
Controlling Flip-Chip Techniques For Concurrent Ball Bonds In Semiconductor Devices
US Patent:
7776653, Aug 17, 2010
Filed:
Jul 2, 2009
Appl. No.:
12/497170
Inventors:
David N Walter - Dallas TX, US
Mark A Gerber - Lucas TX, US
Mark A Gerber - Lucas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/44, H01L 21/48, H01L 21/50
US Classification:
438109, 438612, 438617, 257777
Abstract:
A device has a first semiconductor chip () with contact pads in an interior first set () and a peripheral second set (). A deformed sphere () of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere () is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate () with a chip attachment location and a third set of contact pads () near the location. Low profile bond wires () span between the pads of the third set and the second set. A second semiconductor chip () of a size has a fourth set of contact pads () at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal () bonds the spacers to the second chip, while the spacers space the first and second chips by a gap () wide enough for placing the wire spans to the second set pads.
Method For Fabricating Array-Molded Package-On-Package
US Patent:
2008028, Nov 20, 2008
Filed:
May 18, 2007
Appl. No.:
11/750757
Inventors:
Mark A. Gerber - Plano TX, US
David N. Walter - Dallas TX, US
David N. Walter - Dallas TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
H01L 23/48, B05C 13/00, H01L 21/58
US Classification:
257778, 118503, 438108, 257E2301, 257E21505
Abstract:
A method and apparatus for fabricating a semiconductor device are disclosed. The method attaches semiconductor chips () on a sheet-like insulating substrate () integral with two or more patterned layers of conductive lines and vias and with contact pads () in pad locations. A mold is provided, which has a top portion () with metal protrusions () at locations matching the pad locations. The protrusions are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold cavity. The substrate and the chip are loaded onto the bottom mold portion (); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface. After pressuring encapsulation compound into the cavity, the mold is opened; the encapsulated device has apertures to the pad locations. Any residual compound formed on the pads is removed by laser, plasma, or chemical to expose the metal surface.
Array Molded Package-On-Package Having Redistribution Lines
US Patent:
7944034, May 17, 2011
Filed:
Jun 22, 2007
Appl. No.:
11/767294
Inventors:
Mark A. Gerber - Lucas TX, US
David N. Walter - Dallas TX, US
David N. Walter - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/48, H01L 23/12, B05C 13/00, B22D 19/08
US Classification:
257686, 257E2301, 257E23003, 257E23021, 257E23124, 257E21504, 257E21511, 257778, 257723, 257777, 257680, 257774, 257773
Abstract:
A semiconductor device with a sheet-like insulating substrate () integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads () in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures () at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material () to contact the pads. Metal-filled surface grooves () in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.
Array-Molded Package-On-Package Having Redistribution Lines
US Patent:
8304285, Nov 6, 2012
Filed:
Apr 5, 2011
Appl. No.:
13/080435
Inventors:
Mark A Gerber - Lucas TX, US
David N Walter - Dallas TX, US
David N Walter - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/60
US Classification:
438108, 438107, 438113, 438127, 257680, 257777, 257E21511
Abstract:
A semiconductor device with a sheet-like insulating substrate () integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads () in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures () at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material () to contact the pads. Metal-filled surface grooves () in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.
Two-Metal Layer Ball Grid Array And Chip Scale Package Having Local Interconnects Used In Wire-Bonded And Flip-Chip Semiconductor Assembly
US Patent:
2004021, Nov 4, 2004
Filed:
Feb 12, 2004
Appl. No.:
10/779118
Inventors:
David Walter - Dallas TX, US
Masood Murtuza - Sugarland TX, US
Masood Murtuza - Sugarland TX, US
International Classification:
H01L023/48
US Classification:
257/779000
Abstract:
The present invention comprises a low cost device () and a method () of forming an electrical interconnect between two metal substrate layers configured in a flip-chip format or a wire bonded format. The invention includes a first metal substrate layer (), a second metal substrate layer (), and an organic tape layer () attached therebetween as a dielectric. The organic tape layer () includes a series of spaced apart vias () adapted to receive solder paste (). The second metal layer () includes a plurality of openings () spaced along the surface thereof and coaxially aligned with the spaced vias (). Further, the invention includes a plurality of solder balls () placed across the respective openings () of the second metal layer () such that each solder ball (-) attaches to the solder paste () forming an electrical interconnect running substantially in parallel between the metal layers (). The solder balls are adapted to communicate I/O signals or power to/from an IC supported on the first layer.
Controlling Flip-Chip Techniques For Concurrent Ball Bonds In Semiconductor Devices
US Patent:
7573137, Aug 11, 2009
Filed:
Jun 8, 2006
Appl. No.:
11/423035
Inventors:
David N. Walter - Dallas TX, US
Mark A. Gerber - Lucas TX, US
Mark A. Gerber - Lucas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/48, H01L 23/52, H01L 29/40
US Classification:
257777, 257E23022, 257686
Abstract:
A device has a first semiconductor chip () with contact pads in an interior first set () and a peripheral second set (). A deformed sphere () of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere () is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate () with a chip attachment location and a third set of contact pads () near the location. Low profile bond wires () span between the pads of the third set and the second set. A second semiconductor chip () of a size has a fourth set of contact pads () at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal () bonds the spacers to the second chip, while the spacers space the first and second chips by a gap () wide enough for placing the wire spans to the second set pads.
Method For Fabricating Array-Molded Package-On-Package
US Patent:
2011016, Jul 7, 2011
Filed:
Mar 17, 2011
Appl. No.:
13/050177
Inventors:
Mark A. GERBER - Plano TX, US
David N. WALTER - Dallas TX, US
David N. WALTER - Dallas TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
H01L 21/82, H01L 21/56, H01L 21/782
US Classification:
438107, 438127, 438113, 257E21504, 257E21599, 257E21602
Abstract:
An improved semiconductor device package is manufactured by attaching semiconductor chips () on an insulating substrate () having contact pads (). A mold is provided, which has a top portion () with metal protrusions () at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.
Method For Fabricating Array-Molded Package-On-Package
US Patent:
2014003, Jan 30, 2014
Filed:
Oct 1, 2013
Appl. No.:
14/043305
Inventors:
David N. Walter - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/00
US Classification:
438113
Abstract:
An improved method for fabricating a semiconductor device provides a mold having a top portion and a bottom portion. The top portion includes recesses suitable for a cavity and a plurality of protrusions shaped as truncated cones. A thin sheet of compliant inert polymer is placed over the surface of the top portion. A molding compound is introduced into the cavity to form a encapsulation body covering a semiconductor chip and linear arrays of contact pads adjacent to the chip. Each conical protrusion matches a contact pad location. The thin sheet of compliant inert polymer is peeled off the top portion. The mold is opened and the encapsulated semiconductor chip is removed.
Method For Fabricating Array-Molded Package-On-Package
US Patent:
8574967, Nov 5, 2013
Filed:
Mar 7, 2013
Appl. No.:
13/789109
Inventors:
David N. Walter - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/00
US Classification:
438126, 438112, 438124, 438127, 26427217
Abstract:
An improved semiconductor device package is manufactured by attaching semiconductor chips () on an insulating substrate () having contact pads (). A mold is provided, which has a top portion () with metal protrusions () at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.