DAVID KELLY
Social Work at Commerce Dr, Saint Paul, MN

License number

Minnesota LP6036

Personal information

See more information about DAVID KELLY at radaris.com

Name

Address

Phone

David Kelly, age 64

5201 Sequoia Dr, Minnetonka, MN 55345

(952) 356-5068

Professional information

See more information about DAVID KELLY at trustoria.com

Chef Ii At Target Logistics

Position:

Chef II at Target Logistics

Location:

Saint Paul, Minnesota

Industry:

Food & Beverages

Work:

Target Logistics - Tioga, North Dakota since Oct 2011 - Chef II Alaska General Seafood - Naknek,Alaska May 2010 - Aug 2010 - Kitchen Supervisor University of Alaska Fairbanks - Toolik Field Station,Alaska Aug 2009 - Nov 2009 - Assistant Cook Doyon Universal Services - Naknek,Alaska Jun 2009 - Jul 2009 - Kitchen Helper The Nook - St. Paul, Minnesota Jan 2007 - Jun 2009 - Cook Shamrocks-Casper & Runyon's - St. Paul,Mn Jan 2007 - Jun 2009 - Sous Chef Raytheon Polar Services - McMurdo Station,Antartica Oct 2004 - Aug 2006 - Production Cook Skinner's Pub and Pizza Factory - Saint Paul, Minnesota Nov 2001 - Oct 2004 - Sous Chef Kimberly Hotel - Halls Creek, Australia Jul 2000 - Nov 2000 - Executive Chef Matso's Broome Brewery - Broome, Australia Apr 2000 - Jul 2000 - Head Chef Tinucci's Restaurant - Newport, Minnesota Mar 1998 - Jan 2000 - Sous Chef Holiday Inn - Austin, Texas Jan 1995 - Jan 1998 - Assistant Food and Beverage Supervisor/Lead Cook Murray's - Minneapolis, Minnesota Jan 1990 - Jan 1995 - Cook Cecil's Deli - Minneapolis, Mn. Mar 1987 - Jan 1995 - Lead Cook

Education:

Universidad Nacional Autónoma de México 2010 - 2010
Universidad de Buenos Aires 2009 - 2009
University of Saint Thomas 1978 - 1981
Universidad de Sevilla 1979 - 1980
Saint Thomas Academy 1974 - 1978

Skills:

Food & Beverage, Culinary Skills, Food, Food Safety, Time Management, Banquets, Cooking, Chef, Sales, Restaurant Management

Write Driver Monitoring And Detection

US Patent:

7969677, Jun 28, 2011

Filed:

Mar 23, 2009

Appl. No.:

12/408847

Inventors:

Jeffrey A. Gleason - Burnsville MN, US
Anamul Hoque - Apple Valley MN, US
David W. Kelly - Eagan MN, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G11B 27/36, G11B 5/02

US Classification:

360 31, 360 68

Abstract:

Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Output Compensated Voltage Regulator, An Ic Including The Same And A Method Of Providing A Regulated Voltage

US Patent:

7990219, Aug 2, 2011

Filed:

Oct 13, 2008

Appl. No.:

12/250427

Inventors:

Jeffrey A. Gleason - Burnsville MN, US
David W. Kelly - Eagan MN, US
Paul Mazur - Cottage Grove MN, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H92M 3/04

US Classification:

330258, 330253

Abstract:

A voltage regulator, a method of regulating voltage and an IC including a voltage regulator. In one embodiment, the voltage regulator includes: (1) a DC precision amplifier configured to generate a DC precision signal based on a reference voltage and a regulated output of the voltage regulator and (2) a response amplifier, coupled in parallel with the DC precision amplifier, configured to generate an error signal based on the reference voltage and the regulated output, the response amplifier further configured to generate the regulated output based on a regulating signal comprised of the error signal and the DC precision signal. The DC precision amplifier may be a CMOS amplifier and the response amplifier may be a NPN amplifier.

Differential High Voltage Level Shifter

US Patent:

8044699, Oct 25, 2011

Filed:

Jul 19, 2010

Appl. No.:

12/804293

Inventors:

David W. Kelly - Eagan MN, US

Assignee:

Polar Semiconductor, Inc. - Bloomington MN

International Classification:

H03L 5/00

US Classification:

327333

Abstract:

A level-shift circuit translates a control signal to a level-shifted output. The level-shift circuit includes a pulse generator circuit for providing Set and Reset pulses based on the control signal and a level-shift circuit for translating the Set and Reset pulses to level-shifted Set and Reset pulses. First and second differential detectors are connected to monitor the level-shifted Set and Reset pulses to provide detection of communicated Set and Reset pulses despite the presence of transients in the level-shift circuit. A gate drive circuit employs the Set and Reset pulses communicated by the differential detectors to generate a gate drive signal.

Apparatus And Method For Controlling Common Mode Voltage Of A Disk Drive Write Head

US Patent:

7701654, Apr 20, 2010

Filed:

Sep 14, 2006

Appl. No.:

11/521568

Inventors:

Jason A. Christianson - Apple Valley MN, US
David W. Kelly - Eagan MN, US
Michael John O'Brien - St. Paul MN, US
Cameron Carroll Rabe - Inver Grove Heights MN, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G11B 5/09

US Classification:

360 46, 360 66, 360 67, 360 68

Abstract:

An apparatus and method for controlling the common mode voltage across a data storage device write head. The write current is supplied by a first plurality of parallel current sources each independently activated to limit the common mode voltage generated across the write head. A plurality of parallel resistive elements responsive to current supplied by a second plurality of parallel current sources bias an output transistor that further controls the write current. Each of the plurality of parallel resistive elements and each of the second plurality of parallel current sources is also independently activated to limiting the common mode voltage generated across the write head.