DAVID JOSEPH SAGER
Pilots at Skyview Dr, Portland, OR

6785803, Aug 31, 2004

Sep 22, 2000

09/667248

Amit A. Merchant - Portland OR
David J. Sager - Portland OR
James D. Allen - Portland OR

Intel Corporation - Santa Clara CA

G06F 938

712219, 712244

A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the instructions are then unloaded from the replay queue for replay or re-execution. For a multi-threaded processor, a stall is detected in one of the threads. Instructions of the stalled thread are temporarily stored in a replay queue, except the oldest instruction of the stalled thread which is allowed to replay or re-execute. This allows other threads to have access to execution and replay resources. Eventually, the oldest instruction will execute and retire, which breaks or releases the stalled thread. The instructions stored in the replay queue are then unloaded from the replay queue.

6735688, May 11, 2004

Feb 14, 2000

09/503853

Michael D. Upton - Portland OR
David J. Sager - Portland OR
Darrell Boggs - Aloha OR
Glenn J. Hinton - Portland OR

Intel Corporation - Santa Clara CA

G06F 900

712218, 712 23, 712219

According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.

6487675, Nov 26, 2002

Feb 2, 2001

09/775383

David J. Sager - Portland OR
Thomas D. Fletcher - Portland OR
Glenn J. Hinton - Portland OR
Michael D. Upton - Portland OR

Intel Corporation - Santa Clara CA

G06F 104

713501, 712 32

A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

6792446, Sep 14, 2004

Feb 1, 2002

10/060264

Amit A. Merchant - Portland OR
Darrell D. Buggs - Aloha OR
David J. Sager - Portland OR

Intel Corporation - Santa Clara CA

G06F 900

709108, 712218, 712219

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e. g. , data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

5828868, Oct 27, 1998

Nov 13, 1996

8/746606

David J. Sager - Portland OR
Thomas D. Fletcher - Portland OR
Glenn J. Hinton - Portland OR
Michael D. Upton - Portland OR

Intel Corporation - Santa Clara CA

G06F 106

395556

A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

7035785, Apr 25, 2006

Dec 28, 2001

10/040582

Edward T. Grochowski - San Jose CA, US
David Sager - Portland OR, US
Vivek Tiwari - San Jose CA, US
Ian Young - Portland OR, US
David J. Ayers - Fremont CA, US

Intel Corporation - Santa Clara CA

G06F 17/50

703 18, 323364, 716 1, 716 6, 713322

A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

2009032, Dec 31, 2009

Jun 30, 2008

12/165186

Zeev Sperber - Zichron Yaakov, IL
David J. Sager - Portland OR, US
Fernando Latorre - Huesca, ES
Ori Lempel - Haifa, IL
Evgeni Krimer - Eilat, IL
Bishara Shomar - Nazareth, IL

G06F 9/305

712217, 712E09018

Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.

7877583, Jan 25, 2011

Nov 7, 2008

12/267394

David W. Burns - Portland OR, US
James D. Allen - Portland OR, US
Michael D. Upton - Portland OR, US
Darrell D. Boggs - Aloha OR, US
David J. Sager - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 9/30

712228

In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

6094717, Jul 25, 2000

Jul 31, 1998

9/126658

Amit A. Merchant - Portland OR
David J. Sager - Portland OR
Darrell D. Boggs - Aloha OR
Michael D. Upton - Portland OR

Intel Corp. - Santa Clara CA

G06F 938

712 32

A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.

6304953, Oct 16, 2001

Jul 31, 1998

9/126657

Alexander Paul Henstrom - Beaverton OR
David J. Sager - Portland OR

Intel Corporation - Santa Clara CA

G06F 1582

712215

One embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the first scheduler and adapted to dispatch a second type of computer instructions. The first type of instructions all have a first latency and the second type of instructions all have a second latency. The first scheduler is skewed relative to the second scheduler so that when the first scheduler dispatches one of the first type of computer instructions having a first latency, the second scheduler will dispatch one of the second type of computer instructions that is dependent on the first type of computer instruction at a time equal to the first latency.