CHUONG MINH LE, MD
Neurology at Jose Figueres Ave, San Jose, CA
License number
California A112526
Category
Neurology
Type
Neuromuscular Medicine
License number
California 43504
Category
Neurology
Type
Neuromuscular Medicine
License number
California MD0000046815
Category
Neurology
Type
Neuromuscular Medicine
License number
California N8208
Category
Neurology
Type
Neuromuscular Medicine
License number
California 44588
Category
Neurology
Type
Neuromuscular Medicine
License number
California MD60213693
Category
Neurology
Type
Neuromuscular Medicine
License number
California 14015
Category
Neurology
Type
Neuromuscular Medicine
License number
California D72710
Category
Neurology
Type
Neuromuscular Medicine
License number
California 4301099409
Category
Neurology
Type
Neuromuscular Medicine
License number
California 262409
Category
Neurology
Type
Neuromuscular Medicine
License number
California TL34068
Category
Neurology
Type
Neuromuscular Medicine
License number
California 10250474
Category
Neurology
Type
Neuromuscular Medicine
License number
California 25MAA08984700
Category
Neurology
Type
Neuromuscular Medicine
License number
California 80126511205
Category
Neurology
Type
Neuromuscular Medicine
License number
California IP970
Category
Neurology
Type
Neurology
Address
Address
2
200 Jose Figueres Ave SUITE 475, San Jose, CA 95116
336 22Nd Ave N, Nashville, TN 37203
336 22Nd Ave N, Nashville, TN 37203
Phone
(615) 346-8182
(615) 829-8950 (Fax)
(615) 829-8950 (Fax)
Personal information
See more information about CHUONG MINH LE at radaris.comName
Address
Phone
4545 Rudisill St, Montclair, CA 91763
5438 Carls Ct, San Jose, CA 95123
5383 Greenbank Ct, San Jose, CA 95118
4809 Bandalin Way, Sacramento, CA 95823
368 Baltimore Way, San Francisco, CA 94112
Professional information
Chuong Le - San Jose, CA
Work:
Jabil Circuit - San Jose, CA
Process Engineer Sanmina SCI - Fremont, CA
Sr. Process Engineer GNSS - San Jose, CA
Process Engineer/Manufacturing Engineer
Process Engineer Sanmina SCI - Fremont, CA
Sr. Process Engineer GNSS - San Jose, CA
Process Engineer/Manufacturing Engineer
Education:
San Jose State University - Santa Clara, CA
BS in Electrical Engineering Mission College - Santa Clara, CA
AS in Engineering Cupertino Technical School
Vietnamese and English
BS in Electrical Engineering Mission College - Santa Clara, CA
AS in Engineering Cupertino Technical School
Vietnamese and English
Chuong Le - San Jose, CA
Work:
Western Digital Corporation - San Jose, CA
Assembly Technician Corwil Technology Coporation - Milpitas, CA
Operator Bizcom Electronic Company - Milpitas, CA
Assembly Extron Company - Fremont, CA
Assembly
Assembly Technician Corwil Technology Coporation - Milpitas, CA
Operator Bizcom Electronic Company - Milpitas, CA
Assembly Extron Company - Fremont, CA
Assembly
Education:
De Anza College
Certificate Evergreen College
High School Diploma
Certificate Evergreen College
High School Diploma
Chuong Le, Louisville KY
Specialties:
Neuromuscular Specialist
Address:
500 S Preston St, Louisville, KY 40202
336 22Nd Ave N, Nashville, TN 37203
200 Jose Figueres Ave, San Jose, CA 95116
336 22Nd Ave N, Nashville, TN 37203
200 Jose Figueres Ave, San Jose, CA 95116
Method For Repairing An Asic Memory With Redundancy Row And Input/Output Lines
US Patent:
6065134, May 16, 2000
Filed:
Mar 30, 1998
Appl. No.:
9/052043
Inventors:
Owen S. Bair - Saratoga CA
Saravana Soundararajan - Sunnyvale CA
Adam Kablanian - San Jose CA
Thomas P. Anderson - Sunnyvale CA
Chuong T. Le - San Jose CA
Saravana Soundararajan - Sunnyvale CA
Adam Kablanian - San Jose CA
Thomas P. Anderson - Sunnyvale CA
Chuong T. Le - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1116, G06F 1200
US Classification:
714 7
Abstract:
A method provides an on-chip repair technique to fix defective row or I/O memory lines in an ASIC memory array with redundancy row or I/O memory lines. The method employs progressive urgency and dynamic repair schemes to optimize the allotted time for repairing defective row and I/O memory lines. Progressive urgency scheme increases the need to repair relative to the available redundancy row or I/O memory lines over the entire repairing time. Dynamic repair executes a mandatory-row or a mandatory-I/O repair as defective row or I/O memory lines are detected. In addition, a recurrence error reroutes the address location of a redundancy memory line to another address location of another redundancy memory line in the event that such redundancy memory line itself is defective, and thus requires further repair.
Built-In Self Repair System For Embedded Memories
US Patent:
5764878, Jun 9, 1998
Filed:
Feb 7, 1996
Appl. No.:
8/597964
Inventors:
Adam Kablanian - San Jose CA
Thomas P. Anderson - Sunnyvale CA
Chuong T. Le - San Jose CA
Owen S. Bair - Saratoga CA
Saravana Soundararajan - Sunnyvale CA
Thomas P. Anderson - Sunnyvale CA
Chuong T. Le - San Jose CA
Owen S. Bair - Saratoga CA
Saravana Soundararajan - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1134
US Classification:
39518205
Abstract:
A built-in self-repair system includes an on-chip clock generator for triggering the repairing process to repair defective memory lines or blocks in a memory array of an ASIC chip. The on-chip clock generator enables the self-repair process to start at the power up of a computer system without a need for an external test-triggering signal. The system includes a built-in self-test circuit that tests for a defective row memory line or a defective I/O memory block. The system further includes a fault-latching-and repair-execution circuit that repairs a row memory line or an I/O memory block. Repairing an IO memory block effectively repairs faults that occur between any two adjacent column shorts within an IO memory block. The preferred repairing scheme adopts a 15N diagnosis to achieve high fault correction so that a large percentage of defective memory cells can be replaced by redundant row memory lines or redundant I/O memory blocks. The defective row memory lines and I/O memory blocks are dynamically repaired as each of the row memory lines and I/O memory blocks undergoes testing to determine if any defective memory cells exist.
Integrated Circuit Margin Stress Test System
US Patent:
2006021, Sep 28, 2006
Filed:
Mar 23, 2005
Appl. No.:
11/089300
Inventors:
Kevin LeClair - Prior Lake MN, US
Thomas Wik - Livermore CA, US
Chuong Le - San Jose CA, US
Hieu Nguyen - San Jose CA, US
Duytan Tran - Los Gatos CA, US
Kevin Bligh - Ione CA, US
Thomas Wik - Livermore CA, US
Chuong Le - San Jose CA, US
Hieu Nguyen - San Jose CA, US
Duytan Tran - Los Gatos CA, US
Kevin Bligh - Ione CA, US
International Classification:
G01R 31/28
US Classification:
714726000
Abstract:
Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system testing includes setting a self-timed control input of the memory system to a predetermined self timed period value; and testing the memory based on the predetermined self timed period value.