Brian Steve Smith
Engineering at Edwards Dr, Plano, TX
License number
Louisiana PE.0025198
Issued Date
Feb 2, 1993
Expiration Date
Sep 30, 2017
Category
Civil Engineer
Type
Electrical and Computer Engineer
Address
Address
3012 Edwards Dr, Plano, TX 75025
Professional information
Brian Smith - Plano, TX
Work:
Beacon Training Services, Inc.
Business Development, Proposals and Writer Companion Data Services (CDS) - Dallas, TX
Business Development and Proposal Management PHNS - Dallas, TX
Business Development, Sales Support and Communications Electronic Data Systems (EDS) - Plano, TX
Product Marketing and Sales Support Electronic Data Systems (EDS) - Plano, TX
Proposals and Business Development US Healthcare EDS - Plano, TX
Transitions and Acquisitions EDS
Human Resources (HR) Employee Relations EDS
Quality Management EDS
Human Resources (HR) Employee Relations EDS
Industrial Engineer EDS
Computer Operator
Business Development, Proposals and Writer Companion Data Services (CDS) - Dallas, TX
Business Development and Proposal Management PHNS - Dallas, TX
Business Development, Sales Support and Communications Electronic Data Systems (EDS) - Plano, TX
Product Marketing and Sales Support Electronic Data Systems (EDS) - Plano, TX
Proposals and Business Development US Healthcare EDS - Plano, TX
Transitions and Acquisitions EDS
Human Resources (HR) Employee Relations EDS
Quality Management EDS
Human Resources (HR) Employee Relations EDS
Industrial Engineer EDS
Computer Operator
Education:
Arizona State University - Tempe, AZ
Bachelor of Science in Biology
Bachelor of Science in Biology
Skills:
Privia Administration, Microsoft Office Suite, Marketing Research, Business Process Outsourcing (BPO), Customer Relationship Management (CRM)
Brian Smith - Plano, TX
Work:
Texas Regional Design Construction
Vice- President/ Senior Manager Texas Regional Design Construction
Vice President Real Estate Hibernia National Bank - New Orleans, LA
Facilities Designer II Hibernia National Bank - New Orleans, LA
Facilities Designer I Robert Coleman and Partners - Baton Rouge, LA
Intern Architect
Vice- President/ Senior Manager Texas Regional Design Construction
Vice President Real Estate Hibernia National Bank - New Orleans, LA
Facilities Designer II Hibernia National Bank - New Orleans, LA
Facilities Designer I Robert Coleman and Partners - Baton Rouge, LA
Intern Architect
Education:
Louisiana State University - Baton Rouge, LA
Bachelor's in Architecture Magnet School
College Prep Baton Rouge High School - Baton Rouge, LA
Bachelor's in Architecture Magnet School
College Prep Baton Rouge High School - Baton Rouge, LA
Method For Controlling A Critical Dimension (Cd) In An Etch Process
US Patent:
6808942, Oct 26, 2004
Filed:
May 23, 2003
Appl. No.:
10/444345
Inventors:
Nital Patel - Plano TX
Brian Smith - Plano TX
Jeffrey S. Hodges - Plano TX
Dale R. Burrows - Wylie TX
Yu-Lun Lin - Plano TX
Brian Smith - Plano TX
Jeffrey S. Hodges - Plano TX
Dale R. Burrows - Wylie TX
Yu-Lun Lin - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2100
US Classification:
438 8, 356630
Abstract:
The present invention provides a method for determining resist trim times in an etch process. In one embodiment of the invention, the method for determining resist trim times includes obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer, in a step , and then obtaining an estimated trim time of the patterned resist layer using the resist profile data and critical dimension data, in steps.
Method For Patterning Sub-Lithographic Features In Semiconductor Manufacturing
US Patent:
7300883, Nov 27, 2007
Filed:
Aug 31, 2004
Appl. No.:
10/930228
Inventors:
Francis G. Celii - Dallas TX, US
Brian A. Smith - Plano TX, US
James Blatchford - Richardson TX, US
Robert Kraft - Plano TX, US
Brian A. Smith - Plano TX, US
James Blatchford - Richardson TX, US
Robert Kraft - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/336, H01L 21/302, H01L 21/461, H01L 21/31, H01L 21/469
US Classification:
438736, 438780, 438302
Abstract:
A method of forming a gate electrode (′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (), for example formed of silicon-rich nitride, is deposited over a polysilicon layer () from which the gate electrode (′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer () is then formed over the hardmask layer (), and photoresist () is photolithographically patterned to define the pattern of the gate electrode (′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist () to the BARC layer (). The remaining elements of the BARC layer () are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer () by an anisotropic etch of that layer, using the trimmed BARC elements () as a mask. The hardmask layer elements (′) then mask the etch of the underlying polysilicon layer (), to define the gate electrodes (′), having gate widths that are narrower than the minimum dimension available through photolithography.
Method To Reduce Transistor Gate To Source/Drain Overlap Capacitance By Incorporation Of Carbon
US Patent:
2007016, Jul 19, 2007
Filed:
Mar 8, 2007
Appl. No.:
11/683721
Inventors:
Majid Mansoori - Dallas TX, US
Alwin Tsao - Garland TX, US
Antonio Pacheco Rotondaro - Dallas TX, US
Brian Smith - Plano TX, US
Alwin Tsao - Garland TX, US
Antonio Pacheco Rotondaro - Dallas TX, US
Brian Smith - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/8238
US Classification:
438199000
Abstract:
The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.
Method To Reduce Transistor Gate To Source/Drain Overlap Capacitance By Incorporation Of Carbon
US Patent:
7199011, Apr 3, 2007
Filed:
Jul 16, 2003
Appl. No.:
10/620492
Inventors:
Majid Movahed Mansoori - Plano TX, US
Alwin Tsao - Garland TX, US
Antonio Luis Pacheco Rotondaro - Dallas TX, US
Brian Ashley Smith - Plano TX, US
Alwin Tsao - Garland TX, US
Antonio Luis Pacheco Rotondaro - Dallas TX, US
Brian Ashley Smith - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/336
US Classification:
438270, 438299, 438303, 257E21092, 257E21115
Abstract:
The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.
Drive Current Improvement From Recessed Sige Incorporation Close To Gate
US Patent:
7244654, Jul 17, 2007
Filed:
Jul 29, 2004
Appl. No.:
10/901568
Inventors:
Pr Chidambaram - Richardson TX, US
Douglas T. Grider - McKinney TX, US
Brian A. Smith - Plano TX, US
Haowen Bu - Plano TX, US
Lindsey Hall - Plano TX, US
Douglas T. Grider - McKinney TX, US
Brian A. Smith - Plano TX, US
Haowen Bu - Plano TX, US
Lindsey Hall - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/336
US Classification:
438300, 438305, 257616, 257E21092
Abstract:
A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown () in the recesses, followed by forming sidewall spacers () over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body () after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.
Layout Modification To Eliminate Line Bending Caused By Line Material Shrinkage
US Patent:
2006029, Dec 28, 2006
Filed:
Jun 24, 2005
Appl. No.:
11/165232
Inventors:
Vladimir Ukraintsev - Allen TX, US
Mark Mason - Dallas TX, US
James Blatchford - Richardson TX, US
Brian Smith - Plano TX, US
Brian Hornung - Richardson TX, US
Dirk Anderson - Richardson TX, US
Mark Mason - Dallas TX, US
James Blatchford - Richardson TX, US
Brian Smith - Plano TX, US
Brian Hornung - Richardson TX, US
Dirk Anderson - Richardson TX, US
International Classification:
H01L 23/58, H01L 21/302
US Classification:
438725000, 257632000
Abstract:
A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature disposed adjacent to an outside of a corner feature.
System For Ion Energy Control During Plasma Processing
US Patent:
6097157, Aug 1, 2000
Filed:
Apr 9, 1998
Appl. No.:
9/057892
Inventors:
Lawrence J. Overzet - Plano TX
Brian A. Smith - Plano TX
Brian A. Smith - Plano TX
Assignee:
Board of Regents, The University of Texas System - Austin TX
International Classification:
H05H 100
US Classification:
31511121
Abstract:
An apparatus and method for controlling the plasma potential of a plasma within a plasma chamber (50) is disclosed. The apparatus and method utilize a Faraday shielded inductive source antenna (60) to generate the plasma within the plasma chamber (50) and an electrically conductive probe (100) that is inserted into the plasma chamber (50) to regulate the plasma potential. By independent biasing of the conductive probe (100), which regulates the plasma potential, the ion energy distribution at a conductive substrate (150) within the plasma chamber (50) may be controlled.
In Situ Hardmask Pullback Using An In Situ Plasma Resist Trim Process
US Patent:
7320927, Jan 22, 2008
Filed:
Oct 20, 2003
Appl. No.:
10/689177
Inventors:
Juanita DeLoach - Plano TX, US
Brian A. Smith - Plano TX, US
Brian A. Smith - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/762
US Classification:
438444, 438424, 438438, 438700, 438701, 438713, 257E21546
Abstract:
The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer and a hardmask layer located over the substrate with plasma, trimming the photoresist layer with a plasma to create an exposed portion of the hardmask layer , removing the exposed portion with a plasma to create a trench guide opening , and creating a trench through the trench guide opening with a plasma.