Jesse O. Englade
Engineering at Westvale Pl, Plano, TX
License number
Louisiana PE.0010949
Issued Date
Jul 11, 1967
Category
Civil Engineer
Address
Address
4 Westvale Pl, Plano, TX 75074
Professional information
Register File For Bit Slice Processor With Simultaneous Accessing Of Plural Memory Array Cells
US Patent:
5165039, Nov 17, 1992
Filed:
Mar 28, 1986
Appl. No.:
6/845725
Inventors:
Jeffrey A. Niehaus - Dallas TX
Jesse O. Englade - Plano TX
Jesse O. Englade - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1200
US Classification:
395800
Abstract:
A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array (86). The array (86) simultaneously outputs two data words in response to two read addresses to sense amps (94) and (98). Data can be written into the memory by storing it in a data latch (100) and addressing it with a separate write address. The separate write address is latched in a write address (108) which is enabled on the rising clock edge by control circuit (114).
Status Output For A Bit Slice Alu
US Patent:
4789957, Dec 6, 1988
Filed:
Mar 28, 1986
Appl. No.:
6/845726
Inventors:
Jeffrey A. Niehaus - Dallas TX
Jesse O. Englade - Plano TX
Jesse O. Englade - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 738
US Classification:
364749
Abstract:
A bit slice processor system includes a bit slice ALU that is cascadable to provide multiple length words. Each of the ALUs provides both command outputs and status outputs. The status outputs are interfaced with each of the package as are the command outputs. Each of the ALUs in the cascaded ALU are controlled by an instruction word to perform a predetermined processing function. Internal status information is processed to generate a command output and a status output. This command is transmitted simultaneously with the status to the remaining packages in the cascaded array to provide processing control.