BRIAN DAVID MCMINN
Pilots at Wyldwood Rd, Austin, TX

5267186, Nov 30, 1993

Jul 23, 1991

7/734762

Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 738

364748

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

5058048, Oct 15, 1991

Apr 2, 1990

7/503819

Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 738

364748

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

4731737, Mar 15, 1988

May 7, 1986

6/860608

David B. Witt - Austin TX
Brian D. McMinn - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 700

364200

A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements. " Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control. As a result, the memory itself can, for example, perform such tasks as sorting and searching, even across memory element boundaries, in a manner which conserves, is faster and more efficient then using, host system resources.

5327571, Jul 5, 1994

Aug 10, 1993

8/104398

Brian D. McMinn - Austin TX
Robert H. Perlman - San Jose CA
Prem Sobel - Pondicherry, IN

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9315, G06F 9312, G06F 930

395800

A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

5053631, Oct 1, 1991

Apr 2, 1990

7/503817

Robert M. Perlman - San Jose CA
Prem Sobel - Sunnyvale CA
Brian D. McMinn - Austin TX
Robert C. Thaden - Austin TX
Glenn A. Tamura - Austin TX
Thomas W. Lynch - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 738

364748

A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.

5077692, Dec 31, 1991

Mar 5, 1990

7/489203

Brian D. McMinn - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 700, G11C 11407

36523006

An apparatus which has storage cells arrayed in a matrix having rows and columns. The apparatus includes row select lines for effecting selection of a first array of the storage cells, and column designation lines for effecting selection of at least one specific storage cell among the selected first array of storage cells. Read lines for enabling reading of the contents of the various storage cells are included, as well as an interface circuit associated with each storage cell for effecting operative connection of respective storage cells to appropriate respective read lines. The interface circuits are selectively operatively connected to the row select lines and the column designation lines according to a predetermined arrangement.

5059818, Oct 22, 1991

Jun 1, 1990

7/532311

David B. Witt - Austin TX
Brian D. McMinn - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H03K 513, H03K 700

307269

There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.