ANTHONY C. WONG, M.D.
Osteopathic Medicine at Saratoga Ave, Saratoga, CA

5576642, Nov 19, 1996

Apr 17, 1995

8/422844

Trung Nguyen - San Jose CA
Anthony Y. Wong - Saratoga CA

LSI Logic Corporation - Milpitas CA

H03K 190185, H03K 190948

326 86

An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit. The receiver includes a receiver transistor having a gate electrically connected to the bus line and producing a current in relation to the received signal, a comparator for comparing a voltage level of the received signal to a reference voltage level and for splitting the current into a first path having a current inversely proportional to the received signal and a second path having a current in proportion to the received signal, an output section for providing the CMOS logic signal at a first logic state when the current in the first path is greater than the current in the second path, and for providing the CMOS logic signal at a second logic state when the current in the first path is less than the current in the second path.

5754060, May 19, 1998

Nov 14, 1996

8/747789

Trung Nguyen - San Jose CA
Anthony Yap Wong - Saratoga CA

H03K 190185, H03K 190948

326 86

An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit. The receiver includes a receiver transistor having a gate electrically connected to the bus line and producing a current in relation to the received signal, a comparator for comparing a voltage level of the received signal to a reference voltage level and for splitting the current into a first path having a current inversely proportional to the received signal and a second path having a current in proportion to the received signal, an output section for providing the CMOS logic signal at a first logic state when the current in the first path is greater than the current in the second path, and for providing the CMOS logic signal at a second logic state when the current in the first path is less than the current in the second path.

5594370, Jan 14, 1997

Apr 17, 1995

8/423637

Trung Nguyen - San Jose CA
Anthony Y. Wong - Saratoga CA

LSI Logic Corporation - Milpitas CA

H03K 190185, H03K 290948

326 86

A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver inverter having an input and an output. The inverter inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

5408146, Apr 18, 1995

Jan 31, 1992

7/828404

Trung Nguyen - San Jose CA
Anthony Y. Wong - Saratoga CA

LSI Logic Corporation - Milpitas CA

H03K 190185, H03K 190948

326 86

A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver invertor having an input and an output. The invertor inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

5491432, Feb 13, 1996

Aug 7, 1992

7/927097

Anthony Y. Wong - Saratoga CA
Eric Chan - Fremont CA
Brian Cheung - San Jose CA
Daniel Wong - San Jose CA

LSI Logic Corporation - Milpitas CA

H03K 190185, H03K 190948

326 86

A CMOS driver circuit which differentially drives a pair of transmission lines at a first terminal in response to a signal on the CMOS driver circuit's input terminal for reception of said signal at a second terminal is provided. The driver circuit has two pairs of drive transistors. Each drive transistor has first and second source/drains and a gate. Each drive transistor pair is connected to one of said transmission line pair, and has a NMOS transistor and a PMOS transistor.

5404033, Apr 4, 1995

Dec 23, 1993

8/174896

Daniel Wong - San Jose CA
Anthony Y. Wong - Saratoga CA

Swift Microelectronics Corporation - San Jose CA

H01L 2710

257202

An embodiment of the present invention is a customizable integrated circuit including a basic cell diffusion of four transistors in a substrate. A first metallization layer includes a plurality of connective strips that electrically connect to the basic cell by a plurality of contacts. A second metallization layer, after a first patterning and chemical etch, comprises an orthogonal matrix of conductors that are electrically connected to corresponding connective strips by a plurality of vias that are respectively positioned at an intersection of orthogonal conductors. A second patterning and chemical etch of the second metallization layer configures the basic cell according to a user's specification.

5764710, Jun 9, 1998

Dec 15, 1995

8/573407

Michael B. Cheng - San Jose CA
Anthony Yap Wong - Saratoga CA
Charles Hsiao - Fremont CA
Belle Wong - San Jose CA

Pericom Semiconductor Corp. - San Jose CA

H04L 700

375371

A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable.

5444397, Aug 22, 1995

Oct 5, 1994

8/318238

Anthony Y. Wong - Saratoga CA
David Kwong - Fremont CA
Lee Yang - Cupertino CA
Charles Hsiao - Fremont CA

Pericom Semiconductor Corp. - San Jose CA

H03K 190175, H03K 1902

326 81

An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry.

6081004, Jun 27, 2000

Mar 27, 1995

8/410375

Anthony Y. Wong - Saratoga CA
Anna Tam - Cupertino CA
Daniel Wong - San Jose CA

LSI Logic Corp. - Milpitas CA

H01L 2710

257205

A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.