ZACHARY T SMITH
Nursing at Pike Peak Ave, Fort Collins, CO
License number
Colorado 754680
Issued Date
Apr 16, 2013
Renew Date
Apr 16, 2013
Expiration Date
Jan 31, 2014
Type
Certified Nurse Aide
Address
Address
1416 Pikes Peak Ave, Fort Collins, CO 80526
Professional information
Model Specific Register Operations
US Patent:
2005022, Oct 13, 2005
Filed:
Apr 7, 2004
Appl. No.:
10/819746
Inventors:
John Maly - Laporte CO, US
Ryan Thompson - Loveland CO, US
Zachary Smith - Fort Collins CO, US
Ryan Thompson - Loveland CO, US
Zachary Smith - Fort Collins CO, US
International Classification:
G06F009/45
US Classification:
703022000
Abstract:
Systems, methodologies, media, and other embodiments associated with manipulating model specific registers are described. One exemplary system embodiment includes a model specific register logic that facilitates manipulating a model specific register so that bits that are irrelevant to a processor simulation are not set for the processor simulation. The exemplary system may also include a data store that is configured to store significance vectors that encode information about (ir)relevant model specific register bits and that facilitate the model specific register logic manipulating a model specific register to a desired initial state.
Object-Oriented Interface To Rtl Model Signals
US Patent:
2006012, Jun 15, 2006
Filed:
Dec 14, 2004
Appl. No.:
11/011409
Inventors:
Zachary Smith - Fort Collins CO, US
John Maly - Laporte CO, US
Ryan Thompson - Loveland CO, US
John Maly - Laporte CO, US
Ryan Thompson - Loveland CO, US
International Classification:
G06F 17/50
US Classification:
703014000
Abstract:
Systems, methodologies, media, and other embodiments associated with an object-oriented interface to register transfer language (RTL) signals are described. One exemplary system embodiment includes logic for acquiring the address of an RTL signal and for providing method level access to the RTL signal. The exemplary system embodiment may also include an object that facilitates establishing a relationship between the RTL signal address and RTL signal name and thus facilitates providing method level access to the RTL signal.
Random Code Generation Using Genetic Algorithms
US Patent:
2005022, Oct 6, 2005
Filed:
May 31, 2005
Appl. No.:
11/141480
Inventors:
Zachary Smith - Fort Collins CO, US
Lee Becker - Fort Collins CO, US
David Heckman - Fort Collins CO, US
Lee Becker - Fort Collins CO, US
David Heckman - Fort Collins CO, US
International Classification:
G06F017/50
US Classification:
716004000
Abstract:
Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files. This process may be repeated to generate configuration files which increasingly exercise microprocessor behaviors which are of interest.
Method And Apparatus For Ordering Test Cases For Regression Testing
US Patent:
7178063, Feb 13, 2007
Filed:
Jul 22, 2003
Appl. No.:
10/624767
Inventors:
Zachary S. Smith - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 11/00
US Classification:
714 38, 717124
Abstract:
A method and apparatus for ordering test cases for regression testing in a regression test system. The regression testing may include executing ordered test cases identified and ordered according to preferences. Each prospective test case may be assigned a result record for retaining previous testing history of the specific test case as well as the design model tested. The test may be selected according to preferences that yield more timely discovery of design bugs. Once ordered, the ordered test cases may be tested against a current design model, which results in test results, at least a portion of which updates the corresponding result record.
Systems And Methods For Verifying Core Determinacy
US Patent:
2005011, May 26, 2005
Filed:
Nov 20, 2003
Appl. No.:
10/718123
Inventors:
Zachary Smith - Fort Collins CO, US
Kevin Safford - Fort Collins CO, US
Jeremy Petsinger - Fort Collins CO, US
Kevin Safford - Fort Collins CO, US
Jeremy Petsinger - Fort Collins CO, US
International Classification:
G06F011/00
US Classification:
714032000
Abstract:
In one embodiment, a core determinacy verification system and a method pertain to extracting data stored in core model structures, comparing the extracted data of one modeled processor core with extracted data of another modeled processor core, determining if any mismatching data will cause core divergence, and facilitating notice of an error if any mismatching data will cause core divergence.
Systems And Methods For Identifying Incomplete Transactions
US Patent:
7519865, Apr 14, 2009
Filed:
May 6, 2004
Appl. No.:
10/839859
Inventors:
John Warren Maly - Laporte CO, US
Ryan Clarence Thompson - Loveland CO, US
Zachary Steven Smith - Fort Collins CO, US
Ryan Clarence Thompson - Loveland CO, US
Zachary Steven Smith - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 11/00
US Classification:
714 33
Abstract:
In one embodiment, a system and method for identifying incomplete transactions includes identifying termination of a test case run on a processor verification system, examining a pending transaction list to identify incomplete transactions, and examining at least one forward progress vector to identify incomplete transactions.
Systems And Methods For Determining Bug Ownership
US Patent:
2005012, Jun 2, 2005
Filed:
Nov 13, 2003
Appl. No.:
10/712572
Inventors:
Zachary Smith - Fort Collins CO, US
John Maly - Laporte CO, US
John Maly - Laporte CO, US
International Classification:
G06F011/00
US Classification:
714038000
Abstract:
Disclosed are systems and methods for determining bug ownership. In one embodiment, a system and a method pertain to generating a database that contains database tokens that relate to identified bugs and that are associated with potential owners, generating input tokens associated with a bug in question, scanning the database for occurrences of the input tokens, and determining an overall probability of ownership of the bug in question for potential owners in the database.
Virtual-Bus Interface And Associated System And Method
US Patent:
2005022, Oct 13, 2005
Filed:
Apr 5, 2004
Appl. No.:
10/818389
Inventors:
Zachary Smith - Fort Collins CO, US
John Maly - Laporte CO, US
Ryan Thompson - Loveland CO, US
John Maly - Laporte CO, US
Ryan Thompson - Loveland CO, US
International Classification:
G06F013/42
US Classification:
710305000
Abstract:
One exemplary system embodiment includes a detection logic that facilitates identifying that a point-to-point transaction is a transaction that is not micro-architecturally implemented and a tracking logic that facilitates tracking the transaction and related packets through the virtual bus interface and that also facilitates producing an error data associated with the non-micro-architecturally implemented transaction.
Speculative Expectation Based Event Verification
US Patent:
7574341, Aug 11, 2009
Filed:
Nov 12, 2003
Appl. No.:
10/712855
Inventors:
John Warren Maly - LaPorte CO, US
Ryan Clarenc Thompson - Loveland CO, US
Zachary Steven Smith - Fort Collins CO, US
Ryan Clarenc Thompson - Loveland CO, US
Zachary Steven Smith - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50, G06F 9/455, G06G 7/48, G06F 13/00, G06F 13/28
US Classification:
703 13, 711137, 703 23
Abstract:
A computer implemented method of verifying events generated by an agent includes detecting a stimulus at an input of the agent and determining whether generation of an event by the agent in response to the stimulus is conditional. An expectation of the event is created based at least in part on the stimulus, wherein the agent is expected to generate the event. The method also includes making the expectation speculative if the generation of the event is conditional.
Systems And Methods For Verifying Lockstep Operation
US Patent:
2005012, Jun 2, 2005
Filed:
Nov 19, 2003
Appl. No.:
10/717253
Inventors:
Zachary Smith - Fort Collins CO, US
Kevin Safford - Fort Collins CO, US
Jeremy Petsinger - Fort Collins CO, US
Kevin Safford - Fort Collins CO, US
Jeremy Petsinger - Fort Collins CO, US
International Classification:
G06F011/00
US Classification:
714043000
Abstract:
In one embodiment, a system and a method for verifying lockstep operation pertain to monitoring interface signals, detecting output of a modeled lockstep block, comparing the detected output with an expected output for the lockstep block relative to a current modeled machine state, and flagging a lockstep block error if the detected output does not match the expected output.