MR. YUN CHUNG WANG
Acupuncture in Los Gatos, CA

6380044, Apr 30, 2002

Apr 12, 2000

09/548326

Somit Talwar - Palo Alto CA
Yun Wang - San Jose CA
Michael O. Thompson - Ithaca NY

Ultratech Stepper, Inc. - San Jose CA

H01L 21336

438308, 438795

A high-speed semiconductor transistor and process for forming same. The process includes forming, in a Si substrate ( ), spaced apart shallow trench isolations (STIs) ( ), and a gate ( ) atop the substrate between the STIs. Then, regions ( ) of the substrate on either side of the gate are either amorphized and doped, or just doped. In certain embodiments of the invention, extension regions ( or ′) and deep drain and deep source regions ( or ′) are formed. In other embodiments, just deep drain and deep source regions ( or ′) are formed. A conformal layer ( ) is then formed atop the substrate, covering the substrate surface ( ) and the gate. The conformal layer can serve to absorb light and/or to distribute heat to the underlying structures. Then, at least one of front-side irradiation ( ) and back-side irradiation ( ) is performed to activate the drain and source regions and, if present, the extensions. Explosive recrystallization ( ) is one mechanism used to achieve dopant activation.

6479821, Nov 12, 2002

Sep 11, 2000

09/659094

Andrew M. Hawryluk - Los Altos Hills CA
Somit Talwar - Palo Alto CA
Yun Wang - San Jose CA
David A. Markle - Saratoga CA
Michael O. Thompson - Ithaca NY

Ultratech Stepper, Inc. - San Jose CA

G03G 516

2503161, 438530

A method, apparatus and system for controlling the amount of heat transferred to a process region ( ) of a workpiece (W) from exposure with a pulse of radiation ( ), which may be in the form of a scanning beam (B), using a thermally induced phase switch layer ( ). The apparatus of the invention is a film stack ( ) having an absorber layer ( ) deposited atop the workpiece, such as a silicon wafer. A portion of the absorber layer covers the process region. The absorber layer absorbs radiation and converts the absorbed radiation into heat. The phase switch layer is deposited above or below the absorber layer. The phase switch layer may comprise one or more thin film layers, and may include a thermal insulator layer and a phase transition layer. Because they are in close proximity, the portion of the phase switch layer covering the process region has a temperature that is close to the temperature of the process region. The phase of the phase switch layer changes from a first phase (e. g.

8466446, Jun 18, 2013

Sep 12, 2012

13/612000

Yun Wang - San Jose CA, US
Vidyut Gopal - Sunnyvale CA, US
Imran Hashim - Saratoga CA, US
Dipankar Pramanik - Saratoga CA, US
Tony Chiag - Campbell CA, US

Intermolecular, Inc. - San Jose CA

H01L 47/00

257 4, 257 2, 257536, 257537, 257761, 257E27006, 257E45003, 257E47001, 365100, 365148, 365163

Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

8614787, Dec 24, 2013

Nov 23, 2010

12/952855

Yun Wang - San Jose CA, US
Tony P. Chiang - Campbell CA, US
Chi-I Lang - Cupertino CA, US

Intermolecular, Inc. - San Jose CA

G01N 21/00

356 72

Simultaneous measurement of an internal quantum efficiency and an external quantum efficiency of a solar cell using an emitter that emits light; a three-way beam splitter that splits the light into solar cell light and reference light, wherein the solar cell light strikes the solar cell; a reference detector that detects the reference light; a reflectance detector that detects reflectance light, wherein the reflectance light comprises a portion of the solar cell light reflected off the solar cell; a source meter operatively coupled to the solar cell; a multiplexer operatively coupled to the solar cell, the reference detector, and the reflectance detector; and a computing device that simultaneously computes the internal quantum efficiency and the external quantum efficiency of the solar cell.

8440990, May 14, 2013

Jun 9, 2011

13/156722

Yun Wang - San Jose CA, US
Tony Chiang - Campbell CA, US
Imran Hashim - Saratoga CA, US

Intermolecular, Inc. - San Jose CA

H01L 29/00

257 1, 257 2, 257 4, 257 43, 257E27047, 257E45001, 365148

Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

2013020, Aug 8, 2013

Feb 7, 2012

13/367662

Hieu Pham - Santa Clara CA, US
Vidyut Gopal - Sunnyvale CA, US
Imran Hashim - Saratoga CA, US
Dipankar Pramanik - Saratoga CA, US
Yun Wang - San Jose CA, US
Hong Sheng Yang - Pleasanton CA, US

Intermolecular, Inc. - San Jose CA

H01L 45/00

257 4, 438381, 257E45003

A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ω cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

2014003, Feb 6, 2014

Sep 4, 2013

14/017942

- Tokyo, JP
Imran Hashim - Saratoga CA, US
Tim Minvielle - San Jose CA, US
Dipankar Pramanik - Saratoga CA, US
Yun Wang - San Jose CA, US
Takeshi Yamaguchi - Kanagawa, JP
Hong Sheng Yang - Pleasanton CA, US

Kabushiki Kaisha Toshiba - Tokyo
Intermolecular Inc. - San Jose CA

H01L 45/00

438382

A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

2011002, Feb 3, 2011

Sep 1, 2010

12/807347

Yun Wang - San Jose CA, US
Shaoyin Chen - San Jose CA, US

Ultratech, Inc. - San Jose CA

H01L 21/263, B23K 26/06, B23K 26/08

438795, 21912165, 21912173, 2191218, 257E21333

Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices; the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices.

2013002, Jan 31, 2013

Feb 17, 2012

13/399530

Yun Wang - San Jose CA, US
Tony P. Chiang - Campbell CA, US
Imran Hashim - Saratoga CA, US

Intermolecular, Inc. - San Jose CA

H01L 45/00

257 4, 257 2, 438382, 257E45003

A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.

8072795, Dec 6, 2011

Oct 28, 2009

12/607898

Yun Wang - San Jose CA, US
Prashant Phatak - San Jose CA, US
Tony Chiang - Campbell CA, US

Intermolecular, Inc. - San Jose CA

G11C 11/00, G11C 11/36

365148, 365175

According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.