YU CHEN
Broker in Cambridge, MA

6825068, Nov 30, 2004

Apr 17, 2001

09/836884

Kevin L. Denis - Beverly Farms MA
Yu Chen - Cambridge MA
Paul S. Drzaic - Lexington MA
Joseph M. Jacobson - Newton Centre MA
Peter T. Kazlas - Sudbury MA

E Ink Corporation - Cambridge MA

H01L 2100

438149, 438155

Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

7365394, Apr 29, 2008

Aug 17, 2004

10/919657

Kevin L Denis - Beverly Farms MA, US
Yu Chen - Cambridge MA, US
Paul S Drzaic - Morgan Hill CA, US
Joseph M Jacobson - Newton Centre MA, US
Peter T Kazlas - Sudbury MA, US

E Ink Corporation - Cambridge MA

H01L 27/01

257347, 257E29117

Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

7030412, Apr 18, 2006

May 5, 2000

09/565413

Paul S. Drzaic - Lexington MA, US
Karl R. Amundson - Cambridge MA, US
Gregg M. Duthaler - Brookline MA, US
Peter T. Kazlas - Sudbury MA, US
Yu Chen - Cambridge MA, US

E Ink Corporation - Cambridge MA

H01L 29/04

257 59, 257 72

A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The semiconductor layer is preferably unpatterned. In various display applications, the geometry of the transistors is selected to provide acceptable leakage currents. In a preferred embodiment, the transistor array is employed in an encapsulated electrophoretic display.

2002006, May 23, 2002

Jul 12, 2001

09/904435

Peter Kazlas - Sudbury MA, US
Yu Chen - Cambridge MA, US
Kevin Denis - Beverly Farms MA, US
Paul Drzaic - Morgan Hill CA, US

H01L031/112, H01L031/036, H01L029/76

257/066000

A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer, having a thickness less than approximately 40 nm. The shared silicon layer extends continuously between the first and second transistors. The silicon layer may consist of unpatterned silicon. Heavily doped material may not be required at metal-silicon contact interfaces.