YOUNG CHO KIM
Pilots at Robert Fowler Way, San Jose, CA

7412122, Aug 12, 2008

Mar 15, 2006

11/376352

Matthew Scott Abrams - San Jose CA, US
Young Gon Kim - San Jose CA, US
Myunghee Lee - San Jose CA, US
Stefano Therisod - Sunnyvale CA, US
Robert Elsheimer - Fort Collins CO, US

Avago Technologies General IP Pte Ltd - Singapore

G02B 6/12

385 14, 257458, 257371

An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.

6795961, Sep 21, 2004

May 6, 2003

10/430148

Lars W. Liebmann - Poughquag NY
Carlos A. Fonseca - Staten Island NY
Ioana Graur - Poughkeepsie NY
Young O. Kim - San Jose CA

International Business Machines Corporation - Armonk NY

G06F 1750

716 19, 719 21

A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

8351239, Jan 8, 2013

Oct 23, 2009

12/604915

Young W. Kim - San Jose CA, US
Glen Rosendale - Palo Alto CA, US

Nantero Inc. - Woburn MA

G11C 11/00

365148, 365207, 365226

A dynamic sense current supply circuit and an associated method for rapidly characterizing a resistive memory array is disclosed. In one embodiment, the disclosed circuit comprises a first and second dynamically programmable current mirror sub-circuit. Responsive to a bank of control signals, each dynamically programmable current mirror sub-circuit provides a dynamically adjustable current scaling factor. These scaling factors are used to scale a supplied reference current to generate a plurality of sense currents which can be used within a plurality of read operations on a resistive memory array. A digital circuit is also provided to sense and store the result of each read operation.

2013006, Mar 14, 2013

Sep 13, 2011

13/231804

Syed A. Mujtaba - Santa Clara CA, US
Kee-Bong Song - Santa Clara CA, US
Xiaowen Wang - Cupertino CA, US
Young Jae Kim - San Jose CA, US
Vinay R. Majjigi - Sunnyvale CA, US
Johnson O. Sebeni - Fremont CA, US
Romain Trilling - Cupertino CA, US
Tahir Shamim - San Jose CA, US
Karthik Anantharaman - Cupertino CA, US

Apple Inc. - Cupertino CA

H04W 52/02

370311

A mobile wireless device adapts receive diversity during discontinuous reception based on downlink signal quality, page indicators and page messages. When the downlink signal quality exceeds a pre-determined threshold, the mobile wireless device decodes a page indicator channel through an initial antenna, and otherwise, decodes a paging channel through the initial antenna without decoding the page indicator channel. The mobile wireless device switches to decoding the paging channel through an alternate antenna when a page indicator decodes as an erasure. When a paging message received through a single antenna decodes with an incorrect error checking code, the mobile wireless devices enables receive diversity through multiple antennas for subsequent decoding. The mobile wireless device switches between single antenna reception and multiple antenna reception based on tracking multiple consecutive error checking code failures and successes.

7378195, May 27, 2008

Jun 28, 2004

10/710224

Ioana Graur - Poughkeepsie NY, US
Young O. Kim - San Jose CA, US
Mark A. Lavin - Katonah NY, US
Lars W. Liebmann - Poughquag NY, US

International Business Machines Corporation - Armonk NY

G03F 1/00

430 5

A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e. g. , cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e. g. , be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.

2013004, Feb 14, 2013

Jan 25, 2012

13/357830

Beomsup Kim - Cupertino CA, US
Young Gon Kim - San Jose CA, US

QUALCOMM INCORPORATED - San Diego CA

H04B 1/40, H04B 1/38, H03B 5/08

455 84, 331167, 455 73

An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

2012020, Aug 9, 2012

Apr 19, 2011

13/089486

Myung Chan Choi - San Jose CA, US
Young Tae Kim - San Jose CA, US
Jung Ju Son - Santa Clara CA, US
Sang-Kyun Han - Sunnyvale CA, US
Sun Hyoung Lee - Seoul, KR

ZMOS TECHNOLOGY, INC. - Sunnyvale CA

G11C 7/10, G11C 7/00

36518905, 365222, 365203

Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.