DR. YAN YAN LI, D.C.
Chiropractic at Main St, Milpitas, CA

7269069, Sep 11, 2007

Jun 2, 2006

11/422034

Yan Li - Milpitas CA, US
Mehrdad Mofidi - Fremont CA, US
Shahzad Khalid - Los Angeles CA, US

SanDisk Corporation - Milpitas CA

G11C 16/04

36518518, 36518512, 36518517

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

8218381, Jul 10, 2012

Nov 24, 2009

12/624595

Yan Li - Milpitas CA, US

SanDisk Technologies Inc. - Plano TX

G11C 11/34

36518919

During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by the selected bit lines is sensed. When a program pulse is applied, voltages of the selected bit lines are set based on the amount of coupling. The bit line voltage is set higher when more coupling is sensed. The amount of coupling experience by a given selected bit line is a function of its proximity to unselected bit lines. One or more coupling thresholds can be used to indicate that a given selected bit line has one or two adjacent unselected bit lines, respectively.

8154923, Apr 10, 2012

May 24, 2011

13/114481

Yan Li - Milpitas CA, US
Seungpil Lee - San Ramon CA, US
Siu Lung Chan - San Jose CA, US

SanDisk Technologies Inc. - Plano TX

G11C 11/34

36518503, 36518512, 36518517, 365 8522, 36518525, 36518533

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

2013012, May 16, 2013

Jan 7, 2013

13/735878

SanDisk Technologies, Inc. - Plano TX, US
Yan Li - Milpitas CA, US

SanDisk Technologies, Inc. - Plano TX

G11C 16/26, G11C 16/04

36518503, 36518518

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.

2014002, Jan 23, 2014

Aug 22, 2013

13/973218

Luca Fasoli - Campbell CA, US
Yan Li - Milpitas CA, US
Tianhong Yan - San Jose CA, US

SANDISK 3D LLC - Milpitas CA

G11C 16/06

36518518

A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

8284606, Oct 9, 2012

Nov 17, 2009

12/620508

Yan Li - Milpitas CA, US

SanDisk Technologies Inc. - Plano TX

G11C 11/34

36518518, 36518503, 36518523

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e. g. , on an adjacent bit line or other location).

8305807, Nov 6, 2012

Jul 9, 2010

12/833167

Grishma Shailesh Shah - Milpitas CA, US
Yan Li - Milpitas CA, US

SanDisk Technologies Inc. - Plano TX

G11C 16/34

36518509, 36518522

Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.

8453036, May 28, 2013

Feb 1, 2010

12/697988

Atul Goel - San Jose CA, US
Yan Li - Sunnyvale CA, US

Network Appliance, Inc. - Sunnyvale CA

H03M 13/00

714763

A storage server resizes an array of mass storage devices and distributes data blocks stored in the array of mass storage devices evenly in a declustered organization across the resized array of mass storage devices. Resizing the array of mass storage devices may include adding a new mass storage device to the array or removing a mass storage device from the array. During resizing a data block is moved from one mass storage device to another mass storage device to minimize the imbalance of parity groups shared by the new mass storage devices in the array, as well as minimize the number of data blocks to be moved to uniformly balance the load across the new mass storage device.

8432732, Apr 30, 2013

Jul 9, 2010

12/833146

Yan Li - Milpitas CA, US
Dana Lee - Saratoga CA, US
Jonathan Huynh - San Jose CA, US

SanDisk Technologies Inc. - Plano TX

G11C 11/34

36518502

Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit.

8427890, Apr 23, 2013

Jun 5, 2012

13/488609

Gopinath Balakrishnan - San Jose CA, US
Luca Fasoli - Campbell CA, US
Yuheng Zhang - Saratoga CA, US
Yan Li - Milpitas CA, US

SanDisk 3D LLC - Milpitas CA

G11C 7/00

36518916, 36518905, 365189011

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.