WILLIAM ROBERT MILLER, AUD.
Audiology at National Ave, Los Gatos, CA

5120992, Jun 9, 1992

Jul 3, 1991

7/725286

William E. Miller - Los Gatos CA
Franklin S. Ho - San Carlos CA

National Semiconductor Corporation - Santa Clara CA

H03K 19003

307270

A single resistance permits a CMOS driver to have output devices that controllably transition "fast off-slow on" and which are not simultaneously on while the driver switches states. The driver's output and supply currents contain reduced harmonics. The resistance is coupled to the gates of the output stage PMOS-NMOS devices, and forms an RC circuit with the intrinsic capacitance at the gates, extending the turn-on transition of the gate drive voltages. Each output device then turns on relatively slowly, but turns off normally. The output current transition times are essentially determined by the resistance and intrinsic capacitances. The resistance is implemented using polysilicon or diffusion, and preferably has a magnitude ten times the on-channel resistance of the input PMOS and NMOS devices driving the output stage. Because the resistance and intrinsic capacitances are essentially temperature and power supply voltage independent, and but slightly process dependent, the current output transition times can be controlled despite CMOS parameter variations. A 3-state embodiment of the CMOS buffer uses parallel coupled PMOS-NMOS devices to switchably couple in the resistance between both output gates when the enable signal is high.

7388404, Jun 17, 2008

Jul 26, 2006

11/493413

William Edward Miller - Los Gatos CA, US

National Semiconductor Corporation - Santa Clara CA

H03K 19/0175

326 82, 326 31

A driver circuit limits the magnitude of the initial wave front launched onto a transmission line to a voltage that is approximately one-half of the supply voltage. Thus, immediately after the initial wave front is reflected from an open circuit receiver, a voltage at the receiver is approximately equal to the supply voltage when a rising voltage is launched, and ground when a falling voltage is launched.

5566344, Oct 15, 1996

May 19, 1995

8/445006

Christopher M. Hall - Redwood City CA
Gary D. Phillips - San Jose CA
William E. Miller - Los Gatos CA
David W. Weinrich - San Jose CA
Richard E. Crippen - Mountain View CA
Robert M. Salter - Saratoga CA

National Semiconductor Corporation - Santa Clara CA

G06F 1576

395800

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die.

4835416, May 30, 1989

Aug 31, 1987

7/091851

William E. Miller - Los Gatos CA

National Semiconductor Corporation - Santa Clara CA

H02H 900, H02H 324, H02H 320, H01L 2978

3072964

The present invention provides power supply load dump protection circuitry for insuring that supply voltages that are applied to the supply pad of a low current logic circuit and which exceed a preselected voltage level are prevented from damaging the logic circuit and also from appearing at an output of the logic circuit. Three circuit areas are protected. An integrated 5V regulated supply circuit is protected by connecting the supply pad to a polysilicon resistor in series with the source of the p-channel MOS output pull up transistor of the regulator circuit, the drain of the driver being connected to the 5V regulated supply pad. 16V low current logic circuits associated with the input pads, output pads and the 5V regulator are protected by connecting the supply pad to a large value polysilicon resistor in series with hte power supply pads of these circuits. 16V high current output signal circuits are protected by connecting the supply pad to the source of the p-channel MOS output pull up transistor of the output circuit, with its drain being connected to the output pad. Each of the p-channel MOS transistors has its gate connected to a detection circuit which, upon detection of load dump transients, turns them off.

5255146, Oct 19, 1993

Aug 29, 1991

7/752036

William E. Miller - Los Gatos CA

National Semiconductor Corporation - Santa Clara CA

H02H 904

361 56

A switching element is connected to an integrated circuit for shunting an ESD pulse away from the integrated circuit features. A plurality of detection circuits responsive to typical ESD waveform characteristics provide logical control of the switching means. In the preferred embodiment, a NAND gate drives the switching element. The first input to the NAND gate is a first RC network having a first time constant that exceeds the characteristic rise time of the typical ESD pulse, but not the characteristic duration of the typical ESD pulse. The second input to the NAND gate is a feedback loop from the NAND gate output. The feedback loop includes a second RC network having a second time constant that exceeds the duration of a noise pulse, a third RC network having a third time constant that approximates the characteristic duration of the typical ESD pulse, and an inverter between the second and third RC networks. Application of the ESD pulse causes the first input to drive the NAND gate, thus turning on the switching element, and if the ESD pulse is still present when the second time constant is exceeded, the switching means is latched on via the second input until the third time constant is exceeded.

5581779, Dec 3, 1996

May 19, 1995

8/445007

Christopher M. Hall - Redwood City CA
Gary D. Phillips - San Jose CA
William E. Miller - Los Gatos CA
David W. Weinrich - San Jose CA
Robert M. Salter - Saratoga CA
Richard E. Crippen - Mountain View CA

National Semiconductor Corporation - Santa Clara CA

G06F 1576

395800

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

4857985, Aug 15, 1989

Dec 15, 1988

7/285290

William E. Miller - Los Gatos CA

National Semiconductor Corporation - Santa Clara CA

H01L 2702

357 42

A field effect transistor has its drain and source regions connected between one of the two supply pads of an operative integrated circuit, the gate of the field effect transistor being connected to the other pad such that the gate is negatively biased during reverse battery to prevent current flow through the circuit in this condition and, hence, to prevent destruction of the circuit. The FET is sized to have minimal voltage drop during normal, forward battery operation of the circuit. The FET can be implemented as either an N-channel or a P-channel device.

6005429, Dec 21, 1999

Jul 17, 1998

9/118283

Freeman Zhong - Fremont CA
William E. Miller - Los Gatos CA

National Semiconductor Corporation - Santa Clara CA

H03K 514

327270

An apparatus for and method of reducing electromagnetic interference of an integrated circuit by providing multiple choking levels are disclosed. A choking circuit includes a choking level select signal generator, a pulse choking circuit connected to the choking level select signal generator, and a modulation control circuit connected to the pulse choking circuit. The choking level is increased when modules of the integrated circuit are less active, which reduces electromagnetic interference. The choking level is decreased when modules of the integrated circuit are more active, which maintains the voltage supplied to the power bus above a desired level.

5657444, Aug 12, 1997

Aug 3, 1995

8/510831

Christopher M. Hall - Redwood City CA
William E. Miller - Los Gatos CA

National Semiconductor Corporation - Santa Clara CA

H04L 1222

395186

A microprocessor which has a secure read only memory is disclosed. The secure read only memory provides for storage of a program and security to protect that program.

5432103, Jul 11, 1995

Dec 23, 1992

7/996807

William E. Miller - Los Gatos CA

National Semiconductor Corporation - Santa Clara CA

H01L 21265

437 29

ROM cell programmed ON has N+ source implant spaced a given distance from the gate with LDD bridging the gap between the N+ source and the N channel. ROM cell programmed OFF has P+ implanted into this gap so as to completely override the LDD in this gap. The P+ prevents the N channel from forming ohmic connection to the N+ source.