William Ralph Phillips, III
Dentist at Westlake Ave, Dallas, TX
License number
Colorado 10289
Issued Date
Aug 13, 2010
Renew Date
Mar 1, 2016
Expiration Date
Feb 28, 2018
Type
Dentist
Address
Address
7203 Westlake Ave, Dallas, TX 75214
Professional information
Sr. Consultant At Avanade
Position:
Sr. Consultant at Avanade
Location:
Dallas/Fort Worth Area
Industry:
Information Technology and Services
Work:
Avanade
- Dallas/Fort Worth Area since Jun 2012
-
Sr. Consultant
Education:
Northwestern Oklahoma State University 1993 - 1995
Southwestern Oklahoma State University 1991 - 1993
Southwestern Oklahoma State University 1991 - 1993
Skills:
Active Directory, VMware, Windows Server, VMware ESX, Disaster Recovery, Microsoft Exchange, Servers, Virtualization, DNS, System Administration, MS Dynamics CRM
Owner At Park Cities Oms
Position:
Owner at Park Cities OMS
Location:
Dallas/Fort Worth Area
Industry:
Medical Practice
Work:
Park Cities OMS
-
Owner
Education:
Baylor College of Medicine 1993 - 2003
DDS, Oral Surgery Texas A&M University System Health Science Center- Baylor College of Dentistry 1993 - 1997
DDS, Oral Surgery Texas A&M University System Health Science Center- Baylor College of Dentistry 1993 - 1997
William Phillips - Dallas, TX
Work:
NXP, Eindhoven, The Netherlands
Analog and Mixed Signal Design Engineer Intel - Mnchen
Analog and Mixed Signal Design Engineer Wipro
Analog and Mixed Signal Design Engineer Cypress Semiconductor - Cork
Analog and Mixed Signal Design Engineer NXP, Graz, Austria
Analog and Mixed Signal Design Engineer Kaney Aerospace - Rockford, IL
Analog and Mixed Signal Design Engineer Sensor Dynamics
Analog and Mixed Signal Design Engineer Maxim - Dallas, TX
Analog and Mixed Signal Design Engineer Texas Instruments - Dallas, TX
Analog and Mixed Signal Design Engineer Dallas Semiconductor - Dallas, TX
Analog and Mixed Signal Design Engineer SGS Thomson (ST) - Livonia, MI
Analog and Mixed Signal Design Engineer Lucas Western - Jamestown, ND
Analog and Mixed Signal Design Engineer Sundstrand - Rockford, IL
Analog and Mixed Signal Design Engineer IBM
Analog and Mixed Signal Design Engineer Marconi
Analog and Mixed Signal Design Engineer
Analog and Mixed Signal Design Engineer Intel - Mnchen
Analog and Mixed Signal Design Engineer Wipro
Analog and Mixed Signal Design Engineer Cypress Semiconductor - Cork
Analog and Mixed Signal Design Engineer NXP, Graz, Austria
Analog and Mixed Signal Design Engineer Kaney Aerospace - Rockford, IL
Analog and Mixed Signal Design Engineer Sensor Dynamics
Analog and Mixed Signal Design Engineer Maxim - Dallas, TX
Analog and Mixed Signal Design Engineer Texas Instruments - Dallas, TX
Analog and Mixed Signal Design Engineer Dallas Semiconductor - Dallas, TX
Analog and Mixed Signal Design Engineer SGS Thomson (ST) - Livonia, MI
Analog and Mixed Signal Design Engineer Lucas Western - Jamestown, ND
Analog and Mixed Signal Design Engineer Sundstrand - Rockford, IL
Analog and Mixed Signal Design Engineer IBM
Analog and Mixed Signal Design Engineer Marconi
Analog and Mixed Signal Design Engineer
Education:
Rockford College - Rockford, IL
MBA Portsmouth University
MS in Electrical and Electronic Engineering
MBA Portsmouth University
MS in Electrical and Electronic Engineering
William Phillips - Dallas, TX
Work:
Veracity - Mesquite, TX
Telephone Sales Representative Thrift Recycling Management - Lakewood, WA
Inventory Control Analyst United Parcel Service - Auburn, WA
Logistics Coordinator United States Army - Fort Lewis, WA
Automated Logistical Specialist
Telephone Sales Representative Thrift Recycling Management - Lakewood, WA
Inventory Control Analyst United Parcel Service - Auburn, WA
Logistics Coordinator United States Army - Fort Lewis, WA
Automated Logistical Specialist
Semiconductors Professional
Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Owner, W. S. Phillips Fine Jewelry
Position:
Owner at W. S. Phillips Fine Jewelry
Location:
Dallas/Fort Worth Area
Industry:
Retail
Work:
W. S. Phillips Fine Jewelry
-
Owner
Low Emi Shutdown Circuit For Modem Applications
US Patent:
6429727, Aug 6, 2002
Filed:
Oct 3, 2000
Appl. No.:
09/678887
Inventors:
Neil Gibson - Richardson TX
Marco Corsi - Allen TX
William A. Phillips - Dallas TX
Marco Corsi - Allen TX
William A. Phillips - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G05F 110
US Classification:
327538, 327539
Abstract:
A low EMI bias current generator for cable modem applications has a distributed output stage with a steering input that controls the amount of bias current flowing through each transistor of a differential pair. A pair of resistors acts as a potentiometer controlling the amount of voltage seen across the input of the differential pair. The resistor pair controls the speed of transfer of bias current from one transistor to another such that the current transfer will take the form of a hyperbolic tangent that will allow a very gentle start-up.
William Ralph Phillips, Dallas TX
Specialties:
Oral Surgeon
Address:
8201 Preston Rd, Dallas, TX 75225
9101 N Central Expy, Dallas, TX 75231
9101 N Central Expy, Dallas, TX 75231
Delay Circuit And Method
US Patent:
RE42250, Mar 29, 2011
Filed:
Aug 10, 2001
Appl. No.:
09/927426
Inventors:
William A. Phillips - Dallas TX, US
Mario Paparo - Catania, IT
Piero Capocelli - Milan, IT
Mario Paparo - Catania, IT
Piero Capocelli - Milan, IT
Assignee:
STMicroelectronics, Inc. - Coppell TX
International Classification:
H03K 5/13
US Classification:
327285, 327263, 327278, 327288
Abstract:
A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.