DR. WILLIAM PETER MARTIN, MD
Osteopathic Medicine at Mcgregor St, Manchester, NH

6317069, Nov 13, 2001

Nov 24, 1999

9/444920

Barry Male - West Granby CT
William Martin - Bedford NH

Texas Instruments Incorporated - Dallas TX

H03M 178, H03M 166

341154

A digital-to-analog converter having a compact "M-2M" binary-weighted ladder structure, where "M" represents an effective resistance inversely proportional to the W/L line ratio of an n-type or p-type metal oxide semiconductor (MOS) device. A reduction in the number of ladder components is accomplished by utilizing the MOS device's inherent switching function in combination with the device's resistive behavior. The ladder is comprised of a plurality of "2M" rungs, one rung for each binary bit, and each rung is comprised of a complementary pair of upper and lower MOS devices series-connected at a common node. Each device in the pair has an effective resistance of 2M ohms and only one is enabled at any given time depending upon the value of the associated binary bit. Permanently enabled MOS devices having an effective resistance of M ohms and interconnecting the common nodes of adjacent binary bit device pairs make up an "M" runner. The rungs are connected in parallel across upper-level and lower-level voltage references and an analog voltage corresponding to a digital word is generated at the common node of the most significant bit device pair.

7478286, Jan 13, 2009

Apr 8, 2005

11/101638

George P. Humphrey - Merrimack NH, US
William Edward Martin - Bedford NH, US

Linear Technology Corporation - Milpitas CA

G06F 11/00

714 43, 714 56

A integrated circuit (IC) implementation of a protection circuit detects and resolves a fault on a bus, such as a stuck-low condition on an I2C bus. The circuit includes logic that detects a fault condition caused by the slave device, e. g. when one or both lines are low for a period longer than a timeout value in the I2C example. Upon detecting the fault condition, the logic disconnects the slave device from the data line and the clock line, for example by activation of switches incorporated in the IC. This typically frees the bus for use by other devices. The logic may also send the slave device one or more clock signals to clear the fault and/or a stop bit when the fault clears to reset the data register in the slave device.