WILLIAM PANEPINTO
Radio and Television Technicians in Tewksbury, MA

4266285, May 5, 1981

Jun 28, 1979

6/052999

William Panepinto - Tewksbury MA

Honeywell Information Systems, Inc. - Waltham MA

G11C 1300

365189

A memory subsystem includes a memory board comprising of a number of memory chips positioned at a corresponding number of physical row locations. The memory chips are one of two types selected to provide a predetermined memory capacity. The board further includes a number of decoder circuits connected to generate a corresponding number of sets of chip select signals in response to address signals applied thereto. These signals are applied through corresponding sets of logic circuits for application to the memory chips of each row. Additionally, logic gating circuits logically combine predetermined chip select signals for generating additional chip select signals. These additional chip select signals are applied through switches, the outputs of which are applied to predetermined ones of the sets of logic circuits. When the switches are positioned in a predetermined manner, the additional chip select signals are directed to only predetermined one of the physical row locations via the sets of logic circuits. In this case, only the predetermined row locations are populated with one of the types of memory chips of much larger capacity.

4340933, Jul 20, 1982

Feb 12, 1979

6/008010

Ming T. Miu - Chelmsford MA
John J. Bradley - Framingham MA
William Panepinto - Tewksbury MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1100, G06F 1300

364200

In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.

4214303, Jul 22, 1980

Dec 22, 1977

5/863093

Thomas F. Joyce - Burlington MA
Thomas O. Holtey - Newton Lower Falls MA
William Panepinto - Tewksbury MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1300

364200

A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.

4303993, Dec 1, 1981

Oct 10, 1979

6/083438

William Panepinto - Tewksbury MA
Chester M. Nibby - Peabody MA

Honeywell Information Systems Inc. - Waltham MA

G11C 1300

365230

A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed. By altering the set of switches, the group of memory present circuits can be conditioned to generate an output signal for indicating that the same increment is present for accessing within any one of a number of different segments thereby enabling the same board to be used in any available address slot position.

4317169, Feb 23, 1982

Feb 14, 1979

6/012081

William Panepinto - Tewksbury MA
Ming T. Miu - Chelmsford MA
Chester M. Nibby - Peabody MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1300

364200

In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

4195341, Mar 25, 1980

Dec 22, 1977

5/863094

Thomas F. Joyce - Burlington MA
William Panepinto - Tewksbury MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1300, G11C 906

364200

A data processing system includes a central processor subsystem, a main memory subsystem and a cache subsystem, all coupled in common to a system bus. During the overall system initialization process, apparatus in the cache subsystem effects the transfer of information from the main memory subsystem to the cache subsystem to load all address locations of the cache subsystem. The transfer of information from the main memory subsystem to the cache subsystem starts from the lowest order address locations in main memory and continues from successive address locations until the cache subsystem is fully loaded. This assures that the cache subsystem contains valid information during normal data processing.

4190885, Feb 26, 1980

Dec 22, 1977

5/863096

Thomas F. Joyce - Burlington MA
William Panepinto - Tewksbury MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1100, G06F 1300

364200

A Data Processing System comprises a central processor unit, a main memory and a cache, all coupled in common to a system bus. The central processor unit is also separately coupled to the cache. Apparatus in cache is responsive to signals received from the central processor unit to initiate a test and verification mode of operation in cache. This mode enables the cache to exercise various logic areas of cache and to indicate to the central processor unit hardware faults.

4167782, Sep 11, 1979

Dec 22, 1977

5/863092

Thomas F. Joyce - Burlington MA
Thomas O. Holtey - Newton Lower Falls MA
William Panepinto - Tewksbury MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1300

364200

A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to main memory which will update a word location in main memory. If that word location is also stored in cache then the word location in cache will be updated in addition to the word location in main memory.