DR. WILLIAM MICHAEL TANDY, PHD
Social Work at Riverpark Ln, Boise, ID

6577018, Jun 10, 2003

Aug 25, 2000

09/648316

William D. Tandy - Boise ID
Matt E. Schwab - Boise ID
Cary J. Baerlocher - Meridian ID

Micron Technology, Inc. - Boise ID

H01L 2328

257787, 257678

An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.

6524881, Feb 25, 2003

Aug 25, 2000

09/645904

William D. Tandy - Boise ID
Bret K. Street - Meridian ID

Micron Technology, Inc. - Boise ID

H01L 2100

438 69, 438 51, 438 54, 438 70

The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogeneous surface for marking subsequent to exposure to electro-magnetic radiation.

6692978, Feb 17, 2004

Mar 6, 2002

10/092188

William D. Tandy - Boise ID
Bret K. Street - Meridian ID

Micron Technology, Inc. - Boise ID

H01L 2100

438 26, 438 14, 438 55, 438118, 438459, 438690, 438900, 438977

The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electro-magnetic radiation.

7094618, Aug 22, 2006

Feb 13, 2004

10/778277

William D. Tandy - Boise ID, US
Bret K. Street - Meridian ID, US

Micron Technology, Inc. - Boise ID

H01L 21/00, H01L 21/44, H01L 21/48, H01L 21/50, H01L 21/46

438 26, 438 55, 438118, 438459

The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.

2005003, Feb 17, 2005

Sep 24, 2004

10/949612

Steven James - Boise ID, US
William Tandy - Boise ID, US
Lori Tandy - Boise ID, US

H01L021/48, H01L023/053

257666000, 438123000

A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced. A method for fabricating semiconductor components includes a molding step performed using the system. A semiconductor component fabricated using the system includes the leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe.

7238543, Jul 3, 2007

Nov 18, 2005

11/282893

William D. Tandy - Boise ID, US
Bret K. Street - Meridian ID, US

Micron Technology, Inc. - Boise ID

H01L 21/00, H01L 21/48, H01L 21/44, H01L 21/50, H01L 21/46

438 26, 438 55, 438118, 438459, 257E23179

A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.

2002009, Jul 25, 2002

Mar 6, 2002

10/092139

William Tandy - Boise ID, US
Bret Street - Meridian ID, US

C23F001/00

216/044000

The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electro-magnetic radiation.

7344921, Mar 18, 2008

Feb 21, 2006

11/358268

William D. Tandy - Boise ID, US
Matt E. Schwab - Boise ID, US
Cary J. Baerlocher - Meridian ID, US

Micron Technology, Inc. - Boise ID

H01L 21/44, H01L 21/48, H01L 21/50

438124, 438123, 438106

An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.

6887740, May 3, 2005

Apr 10, 2003

10/412064

William D. Tandy - Boise ID, US
Matt E. Schwab - Boise ID, US
Cary J. Baerlocher - Meridian ID, US

Micron Technology, Inc. - Boise ID

H01L021/44, H01L021/48, H01L021/50

438124, 438106

An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.

7095097, Aug 22, 2006

Aug 31, 2004

10/931369

William D. Tandy - Boise ID, US
Matt E. Schwab - Boise ID, US
Cary J. Baerlocher - Meridian ID, US

Micron Technology, Inc. - Boise ID

H01L 23/495

257666, 257678, 257787

An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.