WILLIAM LOUIS WALTER
Pilots at Jenness St, Lowell, MA
License number
Massachusetts C1020198
Category
Airmen
Address
Address
92 Jenness St, Lowell, MA 01851
Professional information
Precision Set-Reset Logic Circuit And Method
US Patent:
6429712, Aug 6, 2002
Filed:
Aug 29, 2001
Appl. No.:
09/941875
Inventors:
Thomas A. Gaiser - Amherst NH
Kenneth J. Stern - Newton MA
Farhad Vazehgoo - Tynesborough MA
Vincenzo DiTommaso - Arlington MA
William L. Walter - Lowell MA
Edward B. Hilton - Wayland MA
Kenneth J. Stern - Newton MA
Farhad Vazehgoo - Tynesborough MA
Vincenzo DiTommaso - Arlington MA
William L. Walter - Lowell MA
Edward B. Hilton - Wayland MA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 3037
US Classification:
327217, 327222, 327199
Abstract:
A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.
Charge Pump Dc/Dc Converters With Reduced Input Noise
US Patent:
6411531, Jun 25, 2002
Filed:
Nov 21, 2000
Appl. No.:
09/721600
Inventors:
Samuel H. Nork - Andover MA
William L. Walter - Lowell MA
Steven L. Martin - Lowell MA
William L. Walter - Lowell MA
Steven L. Martin - Lowell MA
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
H02M 318
US Classification:
363 60
Abstract:
A charge pump DC/DC converter with reduced noise at the input voltage source is provided. The present invention includes buck and boost DC/DC converters with added circuitry coupled between the input voltage and the switches which maintains a substantially constant input current on both phases of the charge pump clock. The added circuitry reduces input current variations to provide reduced noise at the input voltage source. Feedback loop circuitry coupled between the output node and the added circuitry varies the current through the switches to control the output current of the DC/DC converter in order to maintain the output voltage at the regulated value. The added circuitry may comprise a variable resistor, current mirror, or current mirrors.
High-Efficiency, Low Noise, Inductorless Step-Down Dc/Dc Converter
US Patent:
6438005, Aug 20, 2002
Filed:
Nov 22, 2000
Appl. No.:
09/721140
Inventors:
William L. Walter - Lowell MA
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
H02M 318
US Classification:
363 60, 363 62
Abstract:
A circuit and method for regulating a voltage by means of a switched capacitor circuit including multiple switches and capacitors. The circuit is operable in a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels. In addition, the circuit provides lower output ripple than conventional charge pumps.
Compensation Technique Providing Stability Over Broad Range Of Output Capacitor Values
US Patent:
7218082, May 15, 2007
Filed:
Jan 21, 2005
Appl. No.:
11/038041
Inventors:
William Louis Walter - Lowell MA, US
Joseph Sinohin Panganiban - Lowell MA, US
Joseph Sinohin Panganiban - Lowell MA, US
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
G05F 1/40
US Classification:
323273
Abstract:
A disclosed amplifier and buffer circuit, for example for a linear voltage regulator, comprises an input gain stage, an integrator and a unity-gain output stage. An output stage compensation scheme enables stable operation over a broad range of output capacitance. For low to moderate output capacitance, the design of the output stage effectively pushes the output pole to high frequencies while an internal pole provided by the integrator is dominant and rolls off the gain at lower frequencies. For high output capacitance, an input impedance of the buffer couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. This input impedance connection may utilize the base-emitter resistance of a bipolar junction transistor connected to the internal node, or the connection may use an MOS transistor and a separate RC circuit.
Bidirectional Power Converters
US Patent:
2009010, Apr 30, 2009
Filed:
Oct 29, 2007
Appl. No.:
11/980182
Inventors:
William Walter - Lowell MA, US
Saupama Das - Somerville MA, US
Saupama Das - Somerville MA, US
International Classification:
H02J 1/00
US Classification:
307 80
Abstract:
Circuits and methods for bidirectional power conversion are provided that allow mobile and other devices to generate power suitable to support multiple modes of operation. The bidirectional power converters of the present invention may operate in both step up and step down configurations rather than having a single dedicated conversion function and use many of the same components thereby reducing converter size and complexity.
Method And Circuit For Driving A Gate Of A Mos Transistor Negative
US Patent:
7224204, May 29, 2007
Filed:
Mar 8, 2005
Appl. No.:
11/073722
Inventors:
William Louis Walter - Lowell MA, US
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
H03K 17/687
US Classification:
327427, 327108, 327535, 326 82
Abstract:
A method and circuit for driving the gate of a MOS transistor having a negative or low threshold voltage negative, in which the driving circuit is formed on a single chip. A negative voltage is generated from a positive voltage to drive the gate of the MOS transistor negative. The MOS transistor may be a native NMOS transistor, and the negative voltage is generated for increasing source-drain impedance of the native NMOS transistor. On the other hand, the MOS transistor may be a PMOS transistor, and the negative voltage is generated for reducing source-drain impedance of the PMOS transistor. The MOS transistor can be used as an open-drain switch or a source follower.
Dual Fet Output Stage With Controlled Output Dv/Dt For Reduced Emi And Input Supply Noise
US Patent:
7511390, Mar 31, 2009
Filed:
Jul 29, 2005
Appl. No.:
11/191968
Inventors:
William Louis Walter - Lowell MA, US
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
B23K 11/24, H02B 1/24
US Classification:
307112, 307115
Abstract:
The slew rate of switching circuits, e. g. for DC to DC converters, is controlled without unduly sacrificing total switching time, by providing a weaker switching transistor in parallel with each stronger main switching transistor. Switching of the weaker transistor is controlled so as to have a slower slew rate in transitions between switch states than transitions of the main transistor. The main transistor switches at a fast rate for efficiency, but the slower transition by the weaker transistor provides a more gradual transition of the voltage at the desired switching node, so as to reduce EMI and/or input supply noise.
Precision Set-Reset Logic Circuit
US Patent:
6326828, Dec 4, 2001
Filed:
Dec 7, 1999
Appl. No.:
9/456748
Inventors:
Thomas A. Gaiser - Amherst NH
Kenneth J. Stern - Newton MA
Farhad Vazehgoo - Tynesborough MA
Vincenzo DiTommaso - Arlington MA
William L. Walter - Lowell MA
Edward B. Hilton - Wayland MA
Kenneth J. Stern - Newton MA
Farhad Vazehgoo - Tynesborough MA
Vincenzo DiTommaso - Arlington MA
William L. Walter - Lowell MA
Edward B. Hilton - Wayland MA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 3037
US Classification:
327217
Abstract:
A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.
Bidirectional Power Converters
US Patent:
8536840, Sep 17, 2013
Filed:
Mar 17, 2009
Appl. No.:
12/405282
Inventors:
William Walter - Lowell MA, US
Sauparna Das - North Chelmsford MA, US
Sauparna Das - North Chelmsford MA, US
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
G05F 1/613, G05F 3/16
US Classification:
323223
Abstract:
Circuits and methods for bidirectional power conversion are provided that allow mobile and other devices to generate power suitable to support multiple modes of operation. The bidirectional power converters of the present invention may operate in both step up and step down configurations rather than having a single dedicated conversion function and use many of the same components thereby reducing converter size and complexity. In some embodiments, the converter of the present invention may be used to provide a power component of a communications link, such as a USB link.
Bidirectional Power Converters
US Patent:
8593115, Nov 26, 2013
Filed:
Aug 12, 2010
Appl. No.:
12/855232
Inventors:
William Walter - Lowell MA, US
Sauparna Das - Somerville MA, US
Sauparna Das - Somerville MA, US
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
G05F 1/613, G05F 3/16
US Classification:
323223, 323222
Abstract:
Circuits and methods for bidirectional power conversion are provided that allow mobile and other devices to generate power suitable to support multiple modes of operation. The bidirectional power converters of the present invention may operate in both step up and step down configurations rather than having a single dedicated conversion function and use many of the same components thereby reducing converter size and complexity.