WILLIAM JOHN RUDIK
Pilots at Sheedy Rd, Vestal, NY

6586352, Jul 1, 2003

Oct 20, 2000

09/693766

Lawrence Robert Blumberg - Johnson City NY
Robert Maynard Japp - Vestal NY
William John Rudik - Vestal NY
John Frank Surowka - Binghamton NY

International Business Machines Corporation - Armonk NY

B32B 2709

442181, 442103, 442247, 442255, 29832

A simple, inexpensive, drillable, reduced CTE laminate and circuitized structure comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0. 05% to 0. 3%, preferably from about 0. 08% to 0. 10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. The method further comprises providing a resin volume percent, woven glass cloth volume percent and metal volume percent of the circuitized structure to be fabricated; selecting a desired CTE for the circuitized structure to be fabricated; and determining the amount of non-woven quartz or non-woven glass mat to be incorporated according to a formula.

6534848, Mar 18, 2003

Sep 7, 2000

09/657194

Terry J. Dornbos - Vestal NY
Mark V. Pierson - Binghamton NY
William J. Rudik - Vestal NY
David L. Thomas - Endicott NY

International Business Machines Corporation - Armonk NY

H01L 2302

257678, 257706

A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate.

5866203, Feb 2, 1999

Jul 9, 1997

8/890527

Bernd Karl Appelt - Apalachin NY
Robert Maynard Japp - Vestal NY
Kostantinos Papathomas - Endicott NY
William John Rudik - Vestal NY

International Business Machines Corporation - Armonk NY

B32B 3108, B32B 700

427217

A method and resultant article are provided which optimize the adhesion of resin to the glass fibers in fiberglass cloth impregnated with a resin and also optimize the adhesion of the impregnated resin to metal sheets laminated to the resin-impregnated cloth. The fiberglass is treated in two or more passes. On the first pass, the fiberglass is impregnated with a first resin which is optimized for adherence to glass fibers and the coated resin is partially cured. In a last pass, the fiberglass is impregnated with a second resin, which is different from said first resin, and is optimized for bonding to metal. The second resin is then partially cured. The first and second resins are selected such that they form a bond with each other when cured.

6096665, Aug 1, 2000

Jul 9, 1997

8/891423

Bernd Karl Appelt - Apalachin NY
Robert Maynard Japp - Vestal NY
Kostantinos Papathomas - Endicott NY
William John Rudik - Vestal NY

International Business Machines Corporation - Armonk NY

B05D 138, B32B 3108

442 62

A method for coating cloth especially fiberglass sheets with a resin and resulting structure is provided. The coating is performed in two steps. In the first step, essentially all of the strands of the fiberglass are coated with the resin solvent mixture as well as most of the interstices or openings, although some of the interstices or openings have holes where the coating does not completely fill in. This first coating is then partially cured to the extent that it will not redissolve in a second coating of the same resin solution. The coated fiberglass with partially cured resin thereon is then given a second coating of the same resin mixture which coats the first coating and fills in any holes in the first coating. This second coating is then partially cured, which advances the cure of the first coating and results in an impregnated fiberglass cloth structure for use as sticker sheets. This substantially reduces pinholing.

6306683, Oct 23, 2001

Mar 16, 2000

9/526569

Jean Dery - Granby, CA
Frank D. Egitto - Binghamton NY
Luis J. Matienzo - Endicott NY
Charles Ouellet - Missisquoi, CA
Luc Ouellet - Bromont, CA
David L. Questad - Vestal NY
William J. Rudik - Vestal NY
Son K. Tran - Endwell NY

International Business Machines Corporation - Armonk NY

H01L 2144, H01L 2148, H01L 2150

438108

A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O. sub. 2 plasma or a microwave-generated Ar and N. sub. 2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously.

6074895, Jun 13, 2000

Sep 23, 1997

8/936032

Jean Dery - Granby, CA
Frank D. Egitto - Binghamton NY
Luis J. Matienzo - Endicott NY
Charles Ouellet - Missisquoi, CA
Luc Ouellet - Bromont, CA
David L. Questad - Vestal NY
William J. Rudik - Vestal NY
Son K. Tran - Endwell NY

International Business Machines Corporation - Armonk NY

H01L 2144, H01L 2148, H01L 2150

438108

A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the a surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O. sub. 2 plasma or a microwave-generated Ar and N. sub. 2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously.

5981880, Nov 9, 1999

Aug 20, 1996

8/699902

Bernd Karl-Heinz Appelt - Apalachin NY
Anilkumar Chinuprasad Bhatt - Johnson City NY
James W. Fuller - Endicott NY
John Matthew Lauffer - Waverly NY
Voya Rista Markovich - Endwell NY
William John Rudik - Vestal NY
William Earl Wilson - Waverly NY

International Business Machines Corporation - Armonk NY

H05K 100

174258

A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

7148566, Dec 12, 2006

Mar 26, 2001

09/817843

John U. Knickerbocker - Hopewell Junction NY, US
Voya R. Markovich - Endwell NY, US
Thomas R. Miller - Endwell NY, US
William J. Rudik - Vestal NY, US

International Business Machines Corporation - Armonk NY

H01L 21/44

257701, 257779, 257781

Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

5955782, Sep 21, 1999

Nov 4, 1997

8/964037

Stephen John Kosteva - Endicott NY
David Michael Passante - Endicott NY
William John Rudik - Vestal NY
David John Russell - Apalachin NY
Jonathan Craig Whitcomb - Endicott NY

International Business Machines Corporation - Armonk NY

H01L 2334

257720

A semiconductor package and method for preparing same to obtain improved die adhesion to organic chip carriers has been developed. A copper die bond pad is coated with a passivation material and attached to an organic card with the same passivation material. A semiconductor die may be adhered to the coated die bond pad with either the same passivation material or a common die bond adhesive. Alternatively, the passivation material is coated only on the portion of the die bond pad where the die is attached, and common die bond adhesive attaches the die bond pad to the organic card.

7259333, Aug 21, 2007

Oct 25, 2004

10/904126

Robert Japp - Vestal NY, US
Gregory Kevern - Endwell NY, US
William Rudik - Vestal NY, US

International Business Machines Corporation - Armonk NY

H05K 1/03

174255, 174262

A laminate circuit structure assembly is provided that comprises at least two modularized circuitized voltage plane subassemblies; optionally an interposer located between each of the subassemblies, and wherein the subassemblies and interposer, if present, are bonded together with a cured dielectric coating. The interposer comprises dielectric layers disposed about an internal electrically conductive layer.