DR. WILLIAM JOHN LYNCH, PH.D.
Social Work at Arch St, Redwood City, CA
License number
California PSY5151
Category
Social Work
Type
Clinical Neuropsychologist
Address
Address
133 Arch St SUITE 4, Redwood City, CA 94062
Phone
(650) 363-1615
(650) 345-4593 (Fax)
(650) 345-4593 (Fax)
Professional information
Dr. William J Lynch, Redwood City CA - PHD
Specialties:
Neuropsychology
Address:
Robert N Pavy MD
133 Arch St STE 4, Redwood City 94062
(650) 365-5850 (Phone)
133 Arch St STE 4, Redwood City 94062
(650) 365-5850 (Phone)
Languages:
English
Hospitals:
Robert N Pavy MD
133 Arch St STE 4, Redwood City 94062
San Mateo Medical Center
222 West 39Th Ave, San Mateo 94403
Sequoia Hospital
170 Alameda De Las Pulgas, Redwood City 94062
133 Arch St STE 4, Redwood City 94062
San Mateo Medical Center
222 West 39Th Ave, San Mateo 94403
Sequoia Hospital
170 Alameda De Las Pulgas, Redwood City 94062
Dynamic Code Motion Optimization And Path Tracing
US Patent:
6487715, Nov 26, 2002
Filed:
Apr 16, 1999
Appl. No.:
09/293076
Inventors:
Joseph I. Chamdani - Santa Clara CA
Gary Lauterbach - Los Altos CA
William Lynch - Woodside CA
Gary Lauterbach - Los Altos CA
William Lynch - Woodside CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 944
US Classification:
717154, 717135, 717159, 717161, 712214, 712219, 712233
Abstract:
A method of reordering instructions. Barrier instructions are determined. The method determines when a processor stall may occur, and hoists subsequent instructions to fill in the stall time. However, instructions are not hoisted above the barrier instructions. Barrier instructions include branch instructions, store and load instructions, and instructions which, if hoisted, cause the number of available registers to be exceeded. The method produces a reordered instruction trace and statistics regarding the effectiveness of the reordering.
William John Lynch, Redwood City CA
Specialties:
Psychologist
Address:
133 Arch St, Redwood City, CA 94062
Processor Having Systolic Array Pipeline For Processing Data Packets
US Patent:
7069372, Jun 27, 2006
Filed:
Jun 20, 2002
Appl. No.:
10/177187
Inventors:
Arthur Leung, Jr. - Saratoga CA, US
Anthony J. Li - San Mateo CA, US
William L. Lynch - Redwood City CA, US
Sharad Mehrotra - San Jose CA, US
Anthony J. Li - San Mateo CA, US
William L. Lynch - Redwood City CA, US
Sharad Mehrotra - San Jose CA, US
Assignee:
CISCO Technology, Inc. - San Jose CA
International Classification:
G06F 1/00
US Classification:
710306, 710 38, 712 10, 712 11, 712 19, 709238
Abstract:
A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc. , for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.
Packet Routing And Switching Device
US Patent:
7382787, Jun 3, 2008
Filed:
Jun 20, 2002
Appl. No.:
10/177496
Inventors:
Peter M. Barnes - Mountain View CA, US
Nikhil Jayaram - Los Altos CA, US
Anthony J. Li - San Mateo CA, US
William L. Lynch - Redwood City CA, US
Sharad Mehrotra - San Jose CA, US
Nikhil Jayaram - Los Altos CA, US
Anthony J. Li - San Mateo CA, US
William L. Lynch - Redwood City CA, US
Sharad Mehrotra - San Jose CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 12/28
US Classification:
370401, 370414, 370473
Abstract:
A method for routing and switching data packets from one or more incoming links to one or more outgoing links of a router. The method comprises receiving a data packet from the incoming link, assigning at least one outgoing link to the data packet based on the destination address of the data packet, and after the assigning operation, storing the data packet in a switching memory based on the assigned outgoing link. The data packet extracted from the switching memory, and transmitted along the assigned outgoing link. The router may include a network processing unit having one or more systolic array pipelines for performing the assigning operation.