WILLIAM JAMES PARRISH
Pilots at Ln Ladera Rd, Santa Barbara, CA

License number
California A1452724
Issued Date
Nov 2015
Expiration Date
Nov 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
4185 La Ladera Rd, Santa Barbara, CA 93110

Professional information

William Parrish Photo 1

Two-Stage Auto-Zero Amplifier Circuit For Electro-Optical Arrays

US Patent:
6803555, Oct 12, 2004
Filed:
Sep 7, 2001
Appl. No.:
09/949320
Inventors:
William J. Parrish - Santa Barbara CA
Naseem Y. Aziz - Goleta CA
Assignee:
Indigo Systems Corporation - Goleta CA
International Classification:
H01J 4014
US Classification:
250214C, 250214 AG, 330308
Abstract:
Two-stage auto-zero amplifier circuits are disclosed, along with methods of auto-zeroing such amplifier circuits. The two-stage auto-zero amplifier circuit may be part of an electronics signal chain coupled to a detector element to process an electronic signal induced by illumination. In an exemplary embodiment, the auto-zero amplifier circuit includes a first stage, which includes a low-noise fixed gain amplifier, capacitively coupled to a second stage, which includes a high gain amplifier. In an exemplary embodiment of a method of auto-zeroing the two-stage auto-zero amplifier circuit, a first terminal of the detector element is decoupled from the auto-zero amplifier circuit, and the first stage of the auto-zero amplifier circuit is locally referenced to a second terminal of the detector element. An auto-zero voltage for the auto-zero amplifier circuit is stored between the first stage of the auto-zero amplifier circuit and the second stage of the auto-zero amplifier circuit.


William Parrish Photo 2

Microbolometer Focal Plane Array Methods And Circuitry

US Patent:
6812465, Nov 2, 2004
Filed:
Feb 27, 2002
Appl. No.:
10/085226
Inventors:
William J. Parrish - Santa Barbara CA
Jeffrey L. Heath - Santa Barbara CA
Naseem Y. Aziz - Goleta CA
Joseph Kostrzewa - Solvang CA
George H. Poe - Goleta CA
Assignee:
Indigo Systems Corporation - Goleta CA
International Classification:
G01J 500
US Classification:
2503381, 2503361
Abstract:
Microbolometer circuitry and methods are disclosed to allow an individual microbolometer or groups of microbolometers, such as a microbolometer focal plane array, to operate over a wide temperature range. Temperature compensation is provided, such as through circuitry and/or calibration methods, to reduce non-uniform behavior over the desired operating temperatures. For example, the relative mismatch in the temperature coefficient of resistance of an active microbolometer and a reference microbolometer is compensated by employing a variable resistor in series with the active microbolometer. The variable resistor can be calibrated over the desired temperature range to minimize the affect of the relative mismatch. Various other circuit implementations, calibration methods, and processing of the microbolometer circuit output can be employed to provide further compensation.


William Parrish Photo 3

Methods And Circuitry For Correcting Temperature-Induced Errors In Microbolometer Focal Plane Array

US Patent:
6028309, Feb 22, 2000
Filed:
Feb 10, 1998
Appl. No.:
9/021714
Inventors:
William J. Parrish - Santa Barbara CA
James T. Woolaway - Goleta CA
Assignee:
Indigo Systems Corporation - Santa Barbara CA
International Classification:
G01J 520, G01J 524
US Classification:
250332
Abstract:
Correction for temperature-induced non-uniformities in the response characteristics of the microbolometers in an infrared focal plane array (FPA) is performed by applying a non-uniform corrective bias to the individual microbolometers. The corrective bias is applied either before or during the bias or integration period during which the detectors are sampled. The bias-correction can be applied to two-dimensional detector multiplexers at each column amplifier input, the reference potential for each column amplifier or the voltage supply for each detector element. The magnitude of each corrective bias is determined by calibrating the detectors at different temperatures and different levels of incident infrared radiation. According to another aspect of this invention, a microbolometer which is thermally-shorted to the substrate on which the read out integrated circuit (ROIC) is formed is used along with the sensing microbolometer to compensate for variations in temperature. In some embodiments, an adjustable voltage is applied to the thermally-shorted microbolometer to provide an offset correction.


William Parrish Photo 4

Charge Coupled Device Open Circuit Image Detector

US Patent:
4479139, Oct 23, 1984
Filed:
Jan 19, 1983
Appl. No.:
6/459281
Inventors:
William J. Parrish - Santa Barbara CA
Assignee:
Santa Barbara Research Center - Goleta CA
International Classification:
H01L 2978, H01L 2714, H01L 3100, H03K 342
US Classification:
357 24
Abstract:
An open circuit photodiode includes a capacitor plate formed monolithically with a forward biased P-N junction diode. The capacitor plate, together with one side of the P-N junction, forms a capacitor which is charged by the photocurrent of the diode. The voltage across the capacitor controls the output current of a charge coupled device (CCD) register. The invention operates in an open circuit configuration so that no net current flows across the diode junction as long as the flux of incident radiation is constant. If the incident radiation flux changes, current flows across the diode junction so that the capacitor is charged (or discharged) to a new voltage level corresponding to the new radiation flux level. As a result, the open circuit voltage of the capacitor modulates as a function of the change in incident radiation flux. The non-linearity inherent in the open circuit voltage response of the diode to incident radiation flux compensates for the nonlinearity in the output current response of the CCD register so that the total response is linear.


William Parrish Photo 5

Method For Wafer Scale Testing Of Redundant Integrated Circuit Dies

US Patent:
5053700, Oct 1, 1991
Filed:
Jun 1, 1990
Appl. No.:
7/532059
Inventors:
William J. Parrish - Santa Barbara CA
Assignee:
Amber Engineering, Inc. - Goleta CA
International Classification:
G01R 3128, G06F 1126
US Classification:
324158R
Abstract:
A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation. Additionally, line protection circuits are provided to prevent destruction of the integrated circuit dies should shorting occur during dicing.


William Parrish Photo 6

Methods And Circuitry For Correcting Temperature-Induced Errors In Microbolometer Focal Plane Array

US Patent:
5756999, May 26, 1998
Filed:
Feb 11, 1997
Appl. No.:
8/799663
Inventors:
William J. Parrish - Santa Barbara CA
James T. Woolaway - Goleta CA
Assignee:
Indigo Systems Corporation - Santa Barbara CA
International Classification:
G01J 520, G01J 524
US Classification:
250332
Abstract:
Correction for temperature-induced non-uniformities in the response characteristics of the microbolometers in an infrared focal plane array (FPA) is performed by applying a non-uniform corrective bias to the individual microbolometers. The corrective bias is applied either before or during the bias or integration period during which the detectors are sampled. The bias-correction can be applied to two-dimensional detector multiplexers at each column amplifier input, the reference potential for each column amplifier or the voltage supply for each detector element. The magnitude of each corrective bias is determined by calibrating the detectors at different temperatures and different levels of incident infrared radiation. According to another aspect of this invention, a microbolometer which is thermally-shorted to the substrate on which the read out integrated circuit (ROIC) is formed is used along with the sensing microbolometer to compensate for variations in temperature. Circuitry for providing on-ROIC substrate temperature control is also described.


William Parrish Photo 7

Microbolometer Focal Plane Array Systems And Methods

US Patent:
7034301, Apr 25, 2006
Filed:
Jan 20, 2004
Appl. No.:
10/761769
Inventors:
William J. Parrish - Santa Barbara CA, US
Naseem Y. Aziz - Goleta CA, US
Eric A. Kurth - Santa Barbara CA, US
John D. Schlesselmann - Goleta CA, US
Assignee:
Indigo Systems Corporation - Goleta CA
International Classification:
G01J 5/00
US Classification:
2503381, 250332, 2503361
Abstract:
Systems and methods for microbolometer focal plane arrays are disclosed. For example, in accordance with an embodiment of the present invention, microbolometer focal plane array circuitry is disclosed for a microbolometer array having shared contacts between adjacent microbolometers. Various techniques may be applied to compensate for non-uniformities, such as for example, to allow operation over a calibrated temperature range.


William Parrish Photo 8

Hybrid Gap Measurement Circuit

US Patent:
7015715, Mar 21, 2006
Filed:
Mar 24, 2003
Appl. No.:
10/395431
Inventors:
William J. Parrish - Santa Barbara CA, US
Jeffrey B. Barton - Goleta CA, US
Naseem Y. Aziz - Goleta CA, US
Adrienne N. Costello - Santa Barbara CA, US
Assignee:
Indigo Systems Corporation - Goleta CA
International Classification:
G01R 31/02
US Classification:
324765, 324763, 3241581
Abstract:
Systems and methods are disclosed for measuring a distance (or gap) between substrates of a hybrid semiconductor. The measurements may be made during a hybridization process to, for example, provide alignment feedback during the hybridization process. The measurements may also be made after the hybridization process to further calibrate the process or to provide information useful for further processing operations.


William Parrish Photo 9

Digitally Programmable Gain Normalization Circuit

US Patent:
5039879, Aug 13, 1991
Filed:
Feb 2, 1990
Appl. No.:
7/473835
Inventors:
William J. Parrish - Goleta CA
Assignee:
Grumman Aerospace Corp. - Bethpage NY
International Classification:
G11C 2702
US Classification:
307353
Abstract:
A digitally programmable gain normalization circuit for normalizing gains among analog signal channels. The gain normalization circuit is comprised of a charge integrator which has a plurality of capacitors to provide selectible capacitance values which determine the gain of a differential amplifier/sample and hold circuit. A programmable gain control register selects the charge integrator capacitance value. Both static and dynamic latches are disclosed for selecting the capacitors to be utilized in the charge integrator.


William Parrish Photo 10

Focal Plane Analog-To-Digital Converter

US Patent:
5084704, Jan 28, 1992
Filed:
Feb 2, 1990
Appl. No.:
7/473742
Inventors:
William J. Parrish - Goleta CA
Assignee:
Grumman Aerospace Corporation - Bethpage NY
International Classification:
H03M 134, H03M 152
US Classification:
341164
Abstract:
An integrated circuit analog-to-digital converter for use on the focal plane of an infrared detector array. The analog-to-digital converter has a sample and hold circuit, a comparator circuit, and a latch circuit. A single slope conversion technique is used to generate digital signals representative of the amplitude of the input analog signal.