WILLIAM J RICHARDSON, DPT, CSCS, SPC
Physical Therapy at Sunset Rd, San Antonio, TX
License number
Texas 1265069
Category
Restorative Service Providers
Type
Physical Therapist
Address
Address
414 W Sunset Rd STE 110, San Antonio, TX 78209
Phone
(210) 828-7557
Personal information
See more information about WILLIAM J RICHARDSON at radaris.comName
Address
Phone
520 Willow Oak Dr, Allen, TX 75002
506 Aztec Dr, Robinson, TX 76706
509 N Avenue F, Elgin, TX 78621
Professional information
See more information about WILLIAM J RICHARDSON at trustoria.com
Sige/Poly For Low Resistance Extrinsic Base Npn Transistor
Sige/Poly For Low Resistance Extrinsic Base Npn Transistor
US Patent:
6417058, Jul 9, 2002
Filed:
Jun 14, 2000
Appl. No.:
09/593345
Inventors:
William F. Richardson - San Antonio TX
Yuji Sasaki - San Antonio TX
Yuji Sasaki - San Antonio TX
Assignee:
Sony Corporation - Tokyo
Sony Electronics Inc. - San Diego CA
Sony Electronics Inc. - San Diego CA
International Classification:
H01L 21331
US Classification:
438312, 257197
Abstract:
A low resistance bipolar transistor extrinsic base and method of manufacture. A layer of heavily doped polysilicon is deposited over an oxide layer on an npn silicon substrate and a window is formed through to an n doped region of the substrate. Epitaxial SiGe is grown on the polysilicon layer and within the window. Dopant from the polysilicon layer diffuses into the SiGe layer thereby lowering its resistance.
Capacitor Constructions
Capacitor Constructions
US Patent:
6627938, Sep 30, 2003
Filed:
Dec 1, 2000
Appl. No.:
09/729130
Inventors:
Siang Ping Kwok - Dallas TX
William F. Richardson - San Antonio TX
William F. Richardson - San Antonio TX
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27108
US Classification:
257301, 257303, 257304, 257306, 257308, 257309, 257311
Abstract:
In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.
Tunnel Nitride For Improved Polysilicon Emitter
Tunnel Nitride For Improved Polysilicon Emitter
US Patent:
6228732, May 8, 2001
Filed:
Dec 22, 1999
Appl. No.:
9/470388
Inventors:
William F. Richardson - San Antonio TX
Anhkim Duong - San Antonio TX
Anhkim Duong - San Antonio TX
Assignee:
Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ
Sony Electronics Inc. - Park Ridge NJ
International Classification:
H01L 21331
US Classification:
438342
Abstract:
A method is disclosed for reproducibly and controllably enhancing the current gain of a bipolar junction transistor. Prior to depositing an extrinsic emitter region of polycrystalline silicon, the surface of a monocrystalline silicon substrate is nitridized to grow a layer of silicon nitride thereon. The interfacial layer of silicon nitride functions as a tunnel insulator to enhance the current gain of the transistor and as a diffusion barrier to prevent thickening of the tunnel insulator due to the growth of a native oxide layer while exposed to an oxygen-containing atmosphere. The ubiquitous native silicon oxide on the surface of the monocrystalline silicon substrate may be optionally removed either before nitridation or after nitridation.